DE3856545D1 - Halbleiterbauelement mit isoliertem Gatter - Google Patents

Halbleiterbauelement mit isoliertem Gatter

Info

Publication number
DE3856545D1
DE3856545D1 DE3856545T DE3856545T DE3856545D1 DE 3856545 D1 DE3856545 D1 DE 3856545D1 DE 3856545 T DE3856545 T DE 3856545T DE 3856545 T DE3856545 T DE 3856545T DE 3856545 D1 DE3856545 D1 DE 3856545D1
Authority
DE
Germany
Prior art keywords
semiconductor device
insulated gate
insulated
gate
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE3856545T
Other languages
English (en)
Other versions
DE3856545T2 (de
Inventor
Mutsuhiro Mori
Tomoyuki Tanaka
Yasumichi Yasuda
Yasunori Nakona
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Publication of DE3856545D1 publication Critical patent/DE3856545D1/de
Application granted granted Critical
Publication of DE3856545T2 publication Critical patent/DE3856545T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
    • H01L21/225—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a solid phase, e.g. a doped oxide layer
    • H01L21/2251—Diffusion into or out of group IV semiconductors
    • H01L21/2254—Diffusion into or out of group IV semiconductors from or through or into an applied layer, e.g. photoresist, nitrides
    • H01L21/2257—Diffusion into or out of group IV semiconductors from or through or into an applied layer, e.g. photoresist, nitrides the applied layer being silicon or silicide or SIPOS, e.g. polysilicon, porous silicon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66234—Bipolar junction transistors [BJT]
    • H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
    • H01L29/66333—Vertical insulated gate bipolar transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
    • H01L29/7395—Vertical transistors, e.g. vertical IGBT
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/126—Power FETs
DE3856545T 1987-08-24 1988-08-22 Halbleiterbauelement mit isoliertem Gatter Expired - Lifetime DE3856545T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62208123A JPH0766968B2 (ja) 1987-08-24 1987-08-24 半導体装置及びその製造方法

Publications (2)

Publication Number Publication Date
DE3856545D1 true DE3856545D1 (de) 2002-12-19
DE3856545T2 DE3856545T2 (de) 2003-12-11

Family

ID=16551016

Family Applications (3)

Application Number Title Priority Date Filing Date
DE3856084T Expired - Lifetime DE3856084T2 (de) 1987-08-24 1988-08-22 Verfahren zur Herstellung einer Halbleiteranordnung mit isoliertem Gatter
DE3852444T Expired - Lifetime DE3852444T2 (de) 1987-08-24 1988-08-22 Verfahren zur Herstellung einer Halbleiteranordnung mit isoliertem Gatter.
DE3856545T Expired - Lifetime DE3856545T2 (de) 1987-08-24 1988-08-22 Halbleiterbauelement mit isoliertem Gatter

Family Applications Before (2)

Application Number Title Priority Date Filing Date
DE3856084T Expired - Lifetime DE3856084T2 (de) 1987-08-24 1988-08-22 Verfahren zur Herstellung einer Halbleiteranordnung mit isoliertem Gatter
DE3852444T Expired - Lifetime DE3852444T2 (de) 1987-08-24 1988-08-22 Verfahren zur Herstellung einer Halbleiteranordnung mit isoliertem Gatter.

Country Status (4)

Country Link
US (1) US5032532A (de)
EP (4) EP0604392B1 (de)
JP (1) JPH0766968B2 (de)
DE (3) DE3856084T2 (de)

Families Citing this family (32)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR920003320B1 (ko) * 1988-03-05 1992-04-27 한국과학 기술원 매우 작은 소오스 영역을 갖는 자기 정렬된 수직 이중 확산형 전력 mosfet의 제조방법
US5342797A (en) * 1988-10-03 1994-08-30 National Semiconductor Corporation Method for forming a vertical power MOSFET having doped oxide side wall spacers
JP2689606B2 (ja) * 1989-05-24 1997-12-10 富士電機株式会社 絶縁ゲート電界効果型トランジスタの製造方法
US5262339A (en) * 1989-06-12 1993-11-16 Hitachi, Ltd. Method of manufacturing a power semiconductor device using implants and solid diffusion source
JPH03105978A (ja) * 1989-09-20 1991-05-02 Hitachi Ltd 半導体装置
JP2598328B2 (ja) * 1989-10-17 1997-04-09 三菱電機株式会社 半導体装置およびその製造方法
US5171699A (en) * 1990-10-03 1992-12-15 Texas Instruments Incorporated Vertical DMOS transistor structure built in an N-well CMOS-based BiCMOS process and method of fabrication
US5273934A (en) * 1991-06-19 1993-12-28 Siemens Aktiengesellschaft Method for producing a doped region in a substrate
US5182222A (en) * 1991-06-26 1993-01-26 Texas Instruments Incorporated Process for manufacturing a DMOS transistor
JPH05218436A (ja) * 1992-02-03 1993-08-27 Nec Corp Ｐチャネル縦型ｍｏｓ電界効果トランジスタ
JPH05226352A (ja) * 1992-02-17 1993-09-03 Mitsubishi Electric Corp 半導体装置及びその製造方法
US5753530A (en) * 1992-04-21 1998-05-19 Seiko Instruments, Inc. Impurity doping method with diffusion source of boron-silicide film
US5449886A (en) * 1993-03-09 1995-09-12 University Of Cincinnati Electric heating element assembly
US5369045A (en) * 1993-07-01 1994-11-29 Texas Instruments Incorporated Method for forming a self-aligned lateral DMOS transistor
US5739061A (en) * 1993-10-26 1998-04-14 Fuji Electric Co., Ltd. Method of manufacturing a semiconductor device using gate side wall as mask for self-alignment
JP3186421B2 (ja) * 1994-05-13 2001-07-11 富士電機株式会社 半導体装置の製造方法
DE69429913T2 (de) * 1994-06-23 2002-10-31 St Microelectronics Srl Verfahren zur Herstellung eines Leistungsbauteils in MOS-Technik
US5817546A (en) * 1994-06-23 1998-10-06 Stmicroelectronics S.R.L. Process of making a MOS-technology power device
EP0697739B1 (de) * 1994-08-02 2001-10-31 STMicroelectronics S.r.l. Bipolartransistor mit isolierter Steuerelektrode
US5798554A (en) * 1995-02-24 1998-08-25 Consorzio Per La Ricerca Sulla Microelettronica Nel Mezzogiorno MOS-technology power device integrated structure and manufacturing process thereof
US5518945A (en) * 1995-05-05 1996-05-21 International Business Machines Corporation Method of making a diffused lightly doped drain device with built in etch stop
US5591650A (en) * 1995-06-08 1997-01-07 Taiwan Semiconductor Manufacturing Company Ltd. Method of making a body contacted SOI MOSFET
EP0768714B1 (de) * 1995-10-09 2003-09-17 Consorzio per la Ricerca sulla Microelettronica nel Mezzogiorno - CoRiMMe Herstellungsverfahren für Leistungsanordnung mit Schutzring
EP0772241B1 (de) 1995-10-30 2004-06-09 STMicroelectronics S.r.l. Leistungsbauteil hoher Dichte in MOS-Technologie
DE69534919T2 (de) * 1995-10-30 2007-01-25 Stmicroelectronics S.R.L., Agrate Brianza Leistungsvorrichtung in MOS-Technologie mit einer einzigen kritischen Größe
US6228719B1 (en) 1995-11-06 2001-05-08 Stmicroelectronics S.R.L. MOS technology power device with low output resistance and low capacitance, and related manufacturing process
DE69515876T2 (de) * 1995-11-06 2000-08-17 St Microelectronics Srl Leistungsbauelement in MOS-Technologie mit niedrigem Ausgangswiderstand und geringer Kapazität und dessen Herstellungsverfahren
EP0782201B1 (de) * 1995-12-28 2000-08-30 STMicroelectronics S.r.l. MOS-Technologie-Leistungsanordnung in integrierter Struktur
US5877044A (en) * 1997-03-11 1999-03-02 Harris Corporation Method of making MOS-gated semiconductor devices
EP0961325B1 (de) 1998-05-26 2008-05-07 STMicroelectronics S.r.l. MOS-Technologie-Leistungsanordnung mit hoher Integrationsdichte
JP5025935B2 (ja) * 2005-09-29 2012-09-12 オンセミコンダクター・トレーディング・リミテッド 絶縁ゲート型電界効果トランジスタの製造方法
JP2016029707A (ja) * 2014-07-24 2016-03-03 住友電気工業株式会社 炭化珪素半導体装置

Family Cites Families (30)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3907617A (en) * 1971-10-22 1975-09-23 Motorola Inc Manufacture of a high voltage Schottky barrier device
US4209350A (en) * 1978-11-03 1980-06-24 International Business Machines Corporation Method for forming diffusions having narrow dimensions utilizing reactive ion etching
US4364073A (en) * 1980-03-25 1982-12-14 Rca Corporation Power MOSFET with an anode region
US4691435A (en) * 1981-05-13 1987-09-08 International Business Machines Corporation Method for making Schottky diode having limited area self-aligned guard ring
JPS58115859A (ja) * 1981-12-28 1983-07-09 Fujitsu Ltd 半導体装置の製造方法
US4419809A (en) * 1981-12-30 1983-12-13 International Business Machines Corporation Fabrication process of sub-micrometer channel length MOSFETs
US4419810A (en) * 1981-12-30 1983-12-13 International Business Machines Corporation Self-aligned field effect transistor process
US4445267A (en) * 1981-12-30 1984-05-01 International Business Machines Corporation MOSFET Structure and process to form micrometer long source/drain spacing
NL8105920A (nl) * 1981-12-31 1983-07-18 Philips Nv Halfgeleiderinrichting en werkwijze voor het vervaardigen van een dergelijke halfgeleiderinrichting.
US4598461A (en) * 1982-01-04 1986-07-08 General Electric Company Methods of making self-aligned power MOSFET with integral source-base short
US4503598A (en) * 1982-05-20 1985-03-12 Fairchild Camera & Instrument Corporation Method of fabricating power MOSFET structure utilizing self-aligned diffusion and etching techniques
US4417385A (en) * 1982-08-09 1983-11-29 General Electric Company Processes for manufacturing insulated-gate semiconductor devices with integral shorts
US4466176A (en) * 1982-08-09 1984-08-21 General Electric Company Process for manufacturing insulated-gate semiconductor devices with integral shorts
US4546535A (en) * 1983-12-12 1985-10-15 International Business Machines Corporation Method of making submicron FET structure
US4587713A (en) * 1984-02-22 1986-05-13 Rca Corporation Method for making vertical MOSFET with reduced bipolar effects
JPS6197973A (ja) * 1984-10-19 1986-05-16 Matsushita Electronics Corp Ｍｏｓｆｅｔの製造方法
IT1213234B (it) * 1984-10-25 1989-12-14 Sgs Thomson Microelectronics Procedimento perfezionato per la fabbricazione di dispositivi a semiconduttore dmos.
JPS61156883A (ja) * 1984-12-28 1986-07-16 Toshiba Corp 半導体装置の製造方法
JPS61156882A (ja) * 1984-12-28 1986-07-16 Toshiba Corp 二重拡散形絶縁ゲ−ト電界効果トランジスタ及びその製造方法
US4639754A (en) * 1985-02-25 1987-01-27 Rca Corporation Vertical MOSFET with diminished bipolar effects
EP0202477A3 (de) * 1985-04-24 1988-04-20 General Electric Company Verfahren zum Herstellen elektrischer Kurzschlüsse zwischen benachbarten Gebieten in einer Halbleiteranordnung mit isoliertem Gate
JPS6246570A (ja) * 1985-08-23 1987-02-28 Tdk Corp 縦形半導体装置及びその製造方法
JPS6246568A (ja) * 1985-08-23 1987-02-28 Tdk Corp 縦形半導体装置の製造方法
US4809045A (en) * 1985-09-30 1989-02-28 General Electric Company Insulated gate device
GB8527062D0 (en) * 1985-11-02 1985-12-04 Plessey Co Plc Mos transistor manufacture
JPS62132366A (ja) * 1985-12-04 1987-06-15 Nec Corp 縦型電界効果トランジスタの製造方法
IT1204243B (it) * 1986-03-06 1989-03-01 Sgs Microelettronica Spa Procedimento autoallineato per la fabbricazione di celle dmos di piccole dimensioni e dispositivi mos ottenuti mediante detto procedimento
US4775879A (en) * 1987-03-18 1988-10-04 Motorola Inc. FET structure arrangement having low on resistance
JPH0766966B2 (ja) * 1987-04-06 1995-07-19 株式会社日立製作所 半導体装置
JPH06246568A (ja) * 1993-02-26 1994-09-06 Okuma Mach Works Ltd 自動工具交換中の異常監視方法

Also Published As

Publication number Publication date
US5032532A (en) 1991-07-16
EP0484321A1 (de) 1992-05-06
EP1191600A3 (de) 2002-07-31
EP0304839B1 (de) 1994-12-14
DE3856084D1 (de) 1998-01-22
EP0304839A2 (de) 1989-03-01
EP0304839A3 (en) 1989-08-30
DE3856545T2 (de) 2003-12-11
JPS6451665A (en) 1989-02-27
DE3852444T2 (de) 1995-05-04
DE3856084T2 (de) 1998-08-27
EP1191600A2 (de) 2002-03-27
EP0484321B1 (de) 1997-12-10
JPH0766968B2 (ja) 1995-07-19
DE3852444D1 (de) 1995-01-26
EP0604392B1 (de) 2002-11-13
EP0604392A1 (de) 1994-06-29

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Legal Events

Date Code Title Description
8332 No legal effect for de
8370 Indication of lapse of patent is to be deleted
8364 No opposition during term of opposition