DE3850790D1 - Gatematrix mit in Verbindungsgebiet begrabenem Transistor. - Google Patents

Gatematrix mit in Verbindungsgebiet begrabenem Transistor.

Info

Publication number
DE3850790D1
DE3850790D1 DE3850790T DE3850790T DE3850790D1 DE 3850790 D1 DE3850790 D1 DE 3850790D1 DE 3850790 T DE3850790 T DE 3850790T DE 3850790 T DE3850790 T DE 3850790T DE 3850790 D1 DE3850790 D1 DE 3850790D1
Authority
DE
Germany
Prior art keywords
connection area
gate matrix
transistor buried
buried
transistor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE3850790T
Other languages
English (en)
Other versions
DE3850790T2 (de
Inventor
Hajime Kubosawa
Mitsugo Naitoh
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from JP62027785A external-priority patent/JPS63194348A/ja
Priority claimed from JP23302287A external-priority patent/JPH0750775B2/ja
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Publication of DE3850790D1 publication Critical patent/DE3850790D1/de
Application granted granted Critical
Publication of DE3850790T2 publication Critical patent/DE3850790T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/118—Masterslice integrated circuits
    • H01L27/11803—Masterslice integrated circuits using field effect technology
    • H01L27/11807—CMOS gate arrays
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/535—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including internal interconnections, e.g. cross-under constructions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S257/00—Active solid-state devices, e.g. transistors, solid-state diodes
    • Y10S257/923—Active solid-state devices, e.g. transistors, solid-state diodes with means to optimize electrical conductor current carrying capacity, e.g. particular conductor aspect ratio

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Mathematical Physics (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
DE3850790T 1987-02-09 1988-02-08 Gatematrix mit in Verbindungsgebiet begrabenem Transistor. Expired - Fee Related DE3850790T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP62027785A JPS63194348A (ja) 1987-02-09 1987-02-09 ゲ−トアレイ
JP23302287A JPH0750775B2 (ja) 1987-09-17 1987-09-17 ゲートアレイ

Publications (2)

Publication Number Publication Date
DE3850790D1 true DE3850790D1 (de) 1994-09-01
DE3850790T2 DE3850790T2 (de) 1994-12-22

Family

ID=26365761

Family Applications (1)

Application Number Title Priority Date Filing Date
DE3850790T Expired - Fee Related DE3850790T2 (de) 1987-02-09 1988-02-08 Gatematrix mit in Verbindungsgebiet begrabenem Transistor.

Country Status (4)

Country Link
US (1) US4851891A (de)
EP (1) EP0278463B1 (de)
KR (1) KR900008025B1 (de)
DE (1) DE3850790T2 (de)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2712079B2 (ja) * 1988-02-15 1998-02-10 株式会社東芝 半導体装置
JPH02177457A (ja) * 1988-12-28 1990-07-10 Hitachi Ltd 半導体装置
US5301349A (en) * 1988-12-28 1994-04-05 Kabushiki Kaisha Toshiba Single chip computer having ground wire formed immediately parallel a data bus and drivers formed directly under the data bus for high speed data transfer
JP2721607B2 (ja) * 1991-11-25 1998-03-04 三菱電機株式会社 半導体装置及びその製造方法

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58139446A (ja) * 1982-02-15 1983-08-18 Nec Corp 半導体集積回路装置
JPS5966145A (ja) * 1982-10-08 1984-04-14 Toshiba Corp マスタ−スライス半導体装置
KR890004568B1 (ko) * 1983-07-09 1989-11-15 후지쑤가부시끼가이샤 마스터슬라이스형 반도체장치
JPS6047441A (ja) * 1983-08-26 1985-03-14 Fujitsu Ltd 半導体集積回路
JPS6074644A (ja) * 1983-09-30 1985-04-26 Fujitsu Ltd Ｃｍｏｓゲ−トアレ−

Also Published As

Publication number Publication date
US4851891A (en) 1989-07-25
KR900008025B1 (en) 1990-10-29
DE3850790T2 (de) 1994-12-22
EP0278463A2 (de) 1988-08-17
EP0278463B1 (de) 1994-07-27
KR890013895A (ko) 1989-09-26
EP0278463A3 (en) 1990-05-23

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee