DE3850483D1 - Halbleiterspeicher, der fähig zur Verbesserung der Datenwiedereinschreibgeschwindigkeit ist. - Google Patents

Halbleiterspeicher, der fähig zur Verbesserung der Datenwiedereinschreibgeschwindigkeit ist.

Info

Publication number
DE3850483D1
DE3850483D1 DE3850483T DE3850483T DE3850483D1 DE 3850483 D1 DE3850483 D1 DE 3850483D1 DE 3850483 T DE3850483 T DE 3850483T DE 3850483 T DE3850483 T DE 3850483T DE 3850483 D1 DE3850483 D1 DE 3850483D1
Authority
DE
Germany
Prior art keywords
semiconductor memory
memory capable
data rewriting
improving data
rewriting speed
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE3850483T
Other languages
English (en)
Other versions
DE3850483T2 (de
Inventor
Koichi C O Patent Divis Magome
Masakazu C O Patent Divi Kiryu
Shigeo C O Patent Divi Ohshima
Haruki C O Patent Divisio Toda
Hiroshi C O Patent Divi Sahara
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Toshiba Electronic Device Solutions Corp
Original Assignee
Toshiba Corp
Toshiba Microelectronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from JP62323083A external-priority patent/JPH01165093A/ja
Priority claimed from JP63001653A external-priority patent/JPH0752577B2/ja
Application filed by Toshiba Corp, Toshiba Microelectronics Corp filed Critical Toshiba Corp
Application granted granted Critical
Publication of DE3850483D1 publication Critical patent/DE3850483D1/de
Publication of DE3850483T2 publication Critical patent/DE3850483T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/20—Memory cell initialisation circuits, e.g. when powering up or down, memory clear, latent image memory
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/4072—Circuits for initialization, powering up or down, clearing memory or presetting
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Dram (AREA)
  • Static Random-Access Memory (AREA)
DE3850483T 1987-12-21 1988-12-14 Halbleiterspeicher, der fähig zur Verbesserung der Datenwiedereinschreibgeschwindigkeit ist. Expired - Fee Related DE3850483T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP62323083A JPH01165093A (ja) 1987-12-21 1987-12-21 半導体メモリ
JP63001653A JPH0752577B2 (ja) 1988-01-07 1988-01-07 半導体メモリ

Publications (2)

Publication Number Publication Date
DE3850483D1 true DE3850483D1 (de) 1994-08-04
DE3850483T2 DE3850483T2 (de) 1994-10-20

Family

ID=26334927

Family Applications (1)

Application Number Title Priority Date Filing Date
DE3850483T Expired - Fee Related DE3850483T2 (de) 1987-12-21 1988-12-14 Halbleiterspeicher, der fähig zur Verbesserung der Datenwiedereinschreibgeschwindigkeit ist.

Country Status (5)

Country Link
US (1) US5075887A (de)
EP (1) EP0321847B1 (de)
KR (1) KR920007444B1 (de)
DE (1) DE3850483T2 (de)
MY (1) MY103940A (de)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0430614B1 (de) * 1989-12-01 1996-02-07 Matsushita Electronics Corporation Halbleiterspeicher dynamischen Typs
EP0446847B1 (de) * 1990-03-12 1998-06-17 Nec Corporation Halbleiterspeicheranordnung mit einem verbesserten Schreibmodus
JPH0821233B2 (ja) 1990-03-13 1996-03-04 株式会社東芝 画像メモリおよび画像メモリからデータを読み出す方法
JPH0430388A (ja) * 1990-05-25 1992-02-03 Oki Electric Ind Co Ltd 半導体記憶回路
JPH04188493A (ja) * 1990-11-22 1992-07-07 Mitsubishi Electric Corp 半導体ダイナミックｒａｍ
JP3084801B2 (ja) * 1991-06-27 2000-09-04 日本電気株式会社 半導体メモリ装置
JPH11120797A (ja) * 1997-10-15 1999-04-30 Toshiba Microelectronics Corp 強誘電体メモリ及びそのスクリーニング方法
US7092280B2 (en) * 2004-11-22 2006-08-15 International Business Machines Corp. SRAM with dynamically asymmetric cell

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5785255A (en) * 1980-11-17 1982-05-27 Nec Corp Memory storage for integrated circuit
US4567578A (en) * 1982-09-08 1986-01-28 Harris Corporation Cache memory flush scheme
JPS5958689A (ja) * 1982-09-28 1984-04-04 Fujitsu Ltd 半導体記憶装置
JPS6148192A (ja) * 1984-08-11 1986-03-08 Fujitsu Ltd 半導体記憶装置
EP0189700A3 (de) * 1984-12-28 1988-04-27 Thomson Components-Mostek Corporation Statischer Speicher mit schnellem Nullsetzen
JPS6211977A (ja) * 1985-07-10 1987-01-20 Toshiba Corp 画像メモリ
JPS6265288A (ja) * 1985-09-17 1987-03-24 Matsushita Electric Ind Co Ltd 半導体記憶装置
JPS62121997A (ja) * 1985-11-22 1987-06-03 Hitachi Vlsi Eng Corp ダイナミツク型ｒａｍ
US4837746A (en) * 1985-12-04 1989-06-06 Advanced Micro Devices, Inc. Method and apparatus for resetting a video SRAM
JPS62184693A (ja) * 1986-02-10 1987-08-13 Hitachi Vlsi Eng Corp 半導体記憶装置
JPS62197992A (ja) * 1986-02-25 1987-09-01 Mitsubishi Electric Corp ダイナミツクｒａｍ
US4789967A (en) * 1986-09-16 1988-12-06 Advanced Micro Devices, Inc. Random access memory device with block reset
JPS63247997A (ja) * 1987-04-01 1988-10-14 Mitsubishi Electric Corp 半導体記憶装置
JPH0821234B2 (ja) * 1988-01-14 1996-03-04 三菱電機株式会社 ダイナミック型半導体記憶装置およびその制御方法

Also Published As

Publication number Publication date
DE3850483T2 (de) 1994-10-20
EP0321847A3 (de) 1991-11-06
US5075887A (en) 1991-12-24
EP0321847B1 (de) 1994-06-29
EP0321847A2 (de) 1989-06-28
KR890010916A (ko) 1989-08-11
MY103940A (en) 1993-10-30
KR920007444B1 (ko) 1992-09-01

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee