DE3785317T2 - Matrix hoher Packungsdichte aus dynamischen VMOS RAM. - Google Patents

Matrix hoher Packungsdichte aus dynamischen VMOS RAM.

Info

Publication number
DE3785317T2
DE3785317T2 DE87117303T DE3785317T DE3785317T2 DE 3785317 T2 DE3785317 T2 DE 3785317T2 DE 87117303 T DE87117303 T DE 87117303T DE 3785317 T DE3785317 T DE 3785317T DE 3785317 T2 DE3785317 T2 DE 3785317T2
Authority
DE
Germany
Prior art keywords
trenches
layer
polysilicon
substrate
doped
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE87117303T
Other languages
German (de)
English (en)
Other versions
DE3785317D1 (de
Inventor
Wei Hwang
Stanley Everett Schuster
Lewis Madison Terman
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of DE3785317D1 publication Critical patent/DE3785317D1/de
Application granted granted Critical
Publication of DE3785317T2 publication Critical patent/DE3785317T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/021—Manufacture or treatment of interconnections within wafers or substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/39—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the capacitor and the transistor being in a same trench
    • H10B12/395—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the capacitor and the transistor being in a same trench the transistor being vertical
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D88/00—Three-dimensional [3D] integrated devices
    • H10D88/01—Manufacture or treatment

Landscapes

  • Semiconductor Memories (AREA)
  • Semiconductor Integrated Circuits (AREA)
DE87117303T 1986-12-22 1987-11-24 Matrix hoher Packungsdichte aus dynamischen VMOS RAM. Expired - Fee Related DE3785317T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US06/945,275 US4763180A (en) 1986-12-22 1986-12-22 Method and structure for a high density VMOS dynamic ram array

Publications (2)

Publication Number Publication Date
DE3785317D1 DE3785317D1 (de) 1993-05-13
DE3785317T2 true DE3785317T2 (de) 1993-10-28

Family

ID=25482893

Family Applications (1)

Application Number Title Priority Date Filing Date
DE87117303T Expired - Fee Related DE3785317T2 (de) 1986-12-22 1987-11-24 Matrix hoher Packungsdichte aus dynamischen VMOS RAM.

Country Status (4)

Country Link
US (1) US4763180A (https=)
EP (1) EP0272476B1 (https=)
JP (1) JPS63157463A (https=)
DE (1) DE3785317T2 (https=)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102011052489B4 (de) * 2010-09-20 2013-06-06 Infineon Technologies Ag Verfahren zur Herstellung einer Halbleiterstruktur und Halbleiterstruktur

Families Citing this family (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH088357B2 (ja) * 1986-12-01 1996-01-29 三菱電機株式会社 縦型ｍｏｓトランジスタ
US5734188A (en) * 1987-09-19 1998-03-31 Hitachi, Ltd. Semiconductor integrated circuit, method of fabricating the same and apparatus for fabricating the same
JPH01227468A (ja) * 1988-03-08 1989-09-11 Oki Electric Ind Co Ltd 半導体記憶装置
US4896293A (en) * 1988-06-09 1990-01-23 Texas Instruments Incorporated Dynamic ram cell with isolated trench capacitors
US5917211A (en) * 1988-09-19 1999-06-29 Hitachi, Ltd. Semiconductor integrated circuit, method of fabricating the same and apparatus for fabricating the same
JP3003188B2 (ja) * 1990-09-10 2000-01-24 ソニー株式会社 半導体メモリ及びその製造方法
KR960016773B1 (en) * 1994-03-28 1996-12-20 Samsung Electronics Co Ltd Buried bit line and cylindrical gate cell and forming method thereof
US5693971A (en) * 1994-07-14 1997-12-02 Micron Technology, Inc. Combined trench and field isolation structure for semiconductor devices
US5602049A (en) * 1994-10-04 1997-02-11 United Microelectronics Corporation Method of fabricating a buried structure SRAM cell
DE19620625C1 (de) * 1996-05-22 1997-10-23 Siemens Ag DRAM-Zellenanordnung und Verfahren zu deren Herstellung
US5933725A (en) * 1998-05-27 1999-08-03 Vanguard International Semiconductor Corporation Word line resistance reduction method and design for high density memory with relaxed metal pitch
TW469599B (en) 1998-12-02 2001-12-21 Infineon Technologies Ag DRAM-cells arrangement and its production method
US6380027B2 (en) 1999-01-04 2002-04-30 International Business Machines Corporation Dual tox trench dram structures and process using V-groove
US6271080B1 (en) 1999-12-16 2001-08-07 International Business Machines Corporation Structure and method for planar MOSFET DRAM cell free of wordline gate conductor to storage trench overlay sensitivity
US6437381B1 (en) 2000-04-27 2002-08-20 International Business Machines Corporation Semiconductor memory device with reduced orientation-dependent oxidation in trench structures
KR100473476B1 (ko) * 2002-07-04 2005-03-10 삼성전자주식회사 반도체 장치 및 그 제조방법
US6586291B1 (en) * 2002-08-08 2003-07-01 Lsi Logic Corporation High density memory with storage capacitor
US6853031B2 (en) * 2003-04-17 2005-02-08 United Microelectronics Corp. Structure of a trapezoid-triple-gate FET
EP2555241A1 (en) 2011-08-02 2013-02-06 Nxp B.V. IC die, semiconductor package, printed circuit board and IC die manufacturing method
US9812443B1 (en) 2017-01-13 2017-11-07 International Business Machines Corporation Forming vertical transistors and metal-insulator-metal capacitors on the same chip
CN114927481A (zh) * 2022-05-20 2022-08-19 长鑫存储技术有限公司 半导体结构及其形成方法、存储器

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2619713C2 (de) * 1976-05-04 1984-12-20 Siemens AG, 1000 Berlin und 8000 München Halbleiterspeicher
DE2703871C2 (de) * 1977-01-31 1985-06-13 Siemens AG, 1000 Berlin und 8000 München Halbleiterspeicher mit wenigstens einem V-MOS-Transistor
US4222063A (en) * 1978-05-30 1980-09-09 American Microsystems VMOS Floating gate memory with breakdown voltage lowering region
JPS5511365A (en) * 1978-07-11 1980-01-26 Pioneer Electronic Corp Semiconductor memory
US4225879A (en) * 1979-01-26 1980-09-30 Burroughs Corporation V-MOS Field effect transistor for a dynamic memory cell having improved capacitance
US4369564A (en) * 1979-10-29 1983-01-25 American Microsystems, Inc. VMOS Memory cell and method for making same
JPS5681974A (en) * 1979-12-07 1981-07-04 Toshiba Corp Manufacture of mos type semiconductor device
US4353086A (en) * 1980-05-07 1982-10-05 Bell Telephone Laboratories, Incorporated Silicon integrated circuits
US4364074A (en) * 1980-06-12 1982-12-14 International Business Machines Corporation V-MOS Device with self-aligned multiple electrodes
US4326332A (en) * 1980-07-28 1982-04-27 International Business Machines Corp. Method of making a high density V-MOS memory array
US4672410A (en) * 1984-07-12 1987-06-09 Nippon Telegraph & Telephone Semiconductor memory device with trench surrounding each memory cell
US4651184A (en) * 1984-08-31 1987-03-17 Texas Instruments Incorporated Dram cell and array

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102011052489B4 (de) * 2010-09-20 2013-06-06 Infineon Technologies Ag Verfahren zur Herstellung einer Halbleiterstruktur und Halbleiterstruktur
US10205032B2 (en) 2010-09-20 2019-02-12 Infineon Technologies Ag Semiconductor structure and method for making same

Also Published As

Publication number Publication date
JPH0371786B2 (https=) 1991-11-14
DE3785317D1 (de) 1993-05-13
EP0272476A3 (en) 1989-06-07
US4763180A (en) 1988-08-09
JPS63157463A (ja) 1988-06-30
EP0272476B1 (en) 1993-04-07
EP0272476A2 (en) 1988-06-29

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee