DE3684592D1 - Verfahren zur herstellung eines duennschichttransistors. - Google Patents

Verfahren zur herstellung eines duennschichttransistors.

Info

Publication number
DE3684592D1
DE3684592D1 DE8686310103T DE3684592T DE3684592D1 DE 3684592 D1 DE3684592 D1 DE 3684592D1 DE 8686310103 T DE8686310103 T DE 8686310103T DE 3684592 T DE3684592 T DE 3684592T DE 3684592 D1 DE3684592 D1 DE 3684592D1
Authority
DE
Germany
Prior art keywords
thin
producing
layer transistor
transistor
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE8686310103T
Other languages
English (en)
Inventor
Shunichi Ishihara
Hirokazu Ootoshi
Masaaki Hirooka
Junichi Hanna
Isamu Shimizu
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Canon Inc
Original Assignee
Canon Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Canon Inc filed Critical Canon Inc
Application granted granted Critical
Publication of DE3684592D1 publication Critical patent/DE3684592D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02373—Group 14 semiconducting materials
    • H01L21/02381—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02422—Non-crystalline insulating materials, e.g. glass, polymers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02425—Conductive materials, e.g. metallic silicides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/02433—Crystal orientation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02439—Materials
    • H01L21/02441—Group 14 semiconducting materials
    • H01L21/0245—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02532—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/0262—Reduction or decomposition of gaseous compounds, e.g. CVD
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/057—Gas flow control
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/169—Vacuum deposition, e.g. including molecular beam epitaxy
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/909—Controlled atmosphere
DE8686310103T 1985-12-26 1986-12-23 Verfahren zur herstellung eines duennschichttransistors. Expired - Lifetime DE3684592D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60292312A JPH0746729B2 (ja) 1985-12-26 1985-12-26 薄膜トランジスタの製造方法

Publications (1)

Publication Number Publication Date
DE3684592D1 true DE3684592D1 (de) 1992-04-30

Family

ID=17780139

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8686310103T Expired - Lifetime DE3684592D1 (de) 1985-12-26 1986-12-23 Verfahren zur herstellung eines duennschichttransistors.

Country Status (7)

Country Link
US (1) US4885258A (de)
EP (1) EP0232619B1 (de)
JP (1) JPH0746729B2 (de)
CN (1) CN1007564B (de)
AU (1) AU582033B2 (de)
CA (1) CA1306145C (de)
DE (1) DE3684592D1 (de)

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JPH0746729B2 (ja) * 1985-12-26 1995-05-17 キヤノン株式会社 薄膜トランジスタの製造方法
JP2566914B2 (ja) * 1985-12-28 1996-12-25 キヤノン株式会社 薄膜半導体素子及びその形成法
AU578174B2 (en) * 1985-12-28 1988-10-13 Canon Kabushiki Kaisha Chemical vapor deposition method
NL8801379A (nl) * 1988-05-30 1989-12-18 Imec Inter Uni Micro Electr Werkwijze voor het vervaardigen van een dunne-filmtransistor en een dergelijke dunne-filmtransistor.
JPH02258689A (ja) * 1989-03-31 1990-10-19 Canon Inc 結晶質薄膜の形成方法
JP2805035B2 (ja) * 1990-05-29 1998-09-30 株式会社 半導体エネルギー研究所 薄膜トランジスタ
EP0459763B1 (de) 1990-05-29 1997-05-02 Semiconductor Energy Laboratory Co., Ltd. Dünnfilmtransistoren
JP2700277B2 (ja) * 1990-06-01 1998-01-19 株式会社半導体エネルギー研究所 薄膜トランジスタの作製方法
US5403760A (en) * 1990-10-16 1995-04-04 Texas Instruments Incorporated Method of making a HgCdTe thin film transistor
US5930608A (en) * 1992-02-21 1999-07-27 Semiconductor Energy Laboratory Co., Ltd. Method of fabricating a thin film transistor in which the channel region of the transistor consists of two portions of differing crystallinity
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JPH0815218B2 (ja) * 1991-12-03 1996-02-14 三星電子株式会社 半導体装置の製造方法
JP3173854B2 (ja) 1992-03-25 2001-06-04 株式会社半導体エネルギー研究所 薄膜状絶縁ゲイト型半導体装置の作製方法及び作成された半導体装置
CN100483651C (zh) * 1992-08-27 2009-04-29 株式会社半导体能源研究所 半导体器件的制造方法
US5663077A (en) 1993-07-27 1997-09-02 Semiconductor Energy Laboratory Co., Ltd. Method of manufacturing a thin film transistor in which the gate insulator comprises two oxide films
US6331717B1 (en) 1993-08-12 2001-12-18 Semiconductor Energy Laboratory Co. Ltd. Insulated gate semiconductor device and process for fabricating the same
JP3173926B2 (ja) 1993-08-12 2001-06-04 株式会社半導体エネルギー研究所 薄膜状絶縁ゲイト型半導体装置の作製方法及びその半導体装置
US8119210B2 (en) 2004-05-21 2012-02-21 Applied Materials, Inc. Formation of a silicon oxynitride layer on a high-k dielectric material
US7837838B2 (en) 2006-03-09 2010-11-23 Applied Materials, Inc. Method of fabricating a high dielectric constant transistor gate using a low energy plasma apparatus
US7678710B2 (en) 2006-03-09 2010-03-16 Applied Materials, Inc. Method and apparatus for fabricating a high dielectric constant transistor gate using a low energy plasma system
US7645710B2 (en) 2006-03-09 2010-01-12 Applied Materials, Inc. Method and apparatus for fabricating a high dielectric constant transistor gate using a low energy plasma system
TWI435376B (zh) 2006-09-26 2014-04-21 Applied Materials Inc 用於缺陷鈍化之高ｋ閘極堆疊的氟電漿處理
US20120043543A1 (en) * 2009-04-17 2012-02-23 Sharp Kabushiki Kaisha Semiconductor device and manufacturing method therefor

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JPH0746729B2 (ja) * 1985-12-26 1995-05-17 キヤノン株式会社 薄膜トランジスタの製造方法
JPH084070B2 (ja) * 1985-12-28 1996-01-17 キヤノン株式会社 薄膜半導体素子及びその形成法
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Also Published As

Publication number Publication date
JPS62152171A (ja) 1987-07-07
AU582033B2 (en) 1989-03-09
EP0232619A2 (de) 1987-08-19
CN86108693A (zh) 1987-08-12
JPH0746729B2 (ja) 1995-05-17
EP0232619A3 (en) 1988-04-06
US4885258A (en) 1989-12-05
CN1007564B (zh) 1990-04-11
EP0232619B1 (de) 1992-03-25
AU6691886A (en) 1987-07-02
CA1306145C (en) 1992-08-11

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Legal Events

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