DE3614793A1 - Halbleiterbauelement und dessen herstellung - Google Patents
Halbleiterbauelement und dessen herstellungInfo
- Publication number
- DE3614793A1 DE3614793A1 DE19863614793 DE3614793A DE3614793A1 DE 3614793 A1 DE3614793 A1 DE 3614793A1 DE 19863614793 DE19863614793 DE 19863614793 DE 3614793 A DE3614793 A DE 3614793A DE 3614793 A1 DE3614793 A1 DE 3614793A1
- Authority
- DE
- Germany
- Prior art keywords
- layers
- layer
- semiconductor device
- metal
- silicide
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P95/00—Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
- H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
- H10P14/65—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by treatments performed before or after the formation of the materials
- H10P14/6516—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by treatments performed before or after the formation of the materials of treatments performed after formation of the materials
- H10P14/6518—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by treatments performed before or after the formation of the materials of treatments performed after formation of the materials by introduction of substances into an already-existing insulating layer
- H10P14/6519—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by treatments performed before or after the formation of the materials of treatments performed after formation of the materials by introduction of substances into an already-existing insulating layer the substance being oxygen
- H10P14/6522—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by treatments performed before or after the formation of the materials of treatments performed after formation of the materials by introduction of substances into an already-existing insulating layer the substance being oxygen introduced into a nitride material, e.g. changing SiN to SiON
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/01—Manufacture or treatment
- H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
- H10D30/0223—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
- H10D62/83—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D64/00—Electrodes of devices having potential barriers
- H10D64/60—Electrodes characterised by their materials
- H10D64/62—Electrodes ohmically coupled to a semiconductor
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D64/00—Electrodes of devices having potential barriers
- H10D64/60—Electrodes characterised by their materials
- H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
- H10D64/661—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon having vertical doping variation
- H10D64/662—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon having vertical doping variation the conductor further comprising additional layers, e.g. multiple silicon layers having different crystal structures
- H10D64/663—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon having vertical doping variation the conductor further comprising additional layers, e.g. multiple silicon layers having different crystal structures the additional layers comprising a silicide layer contacting the layer of silicon, e.g. polycide gates
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
- H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
- H10P14/69—Inorganic materials
- H10P14/692—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses
- H10P14/6938—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses the material containing at least one metal element, e.g. metal oxides, metal oxynitrides or metal oxycarbides
- H10P14/6939—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses the material containing at least one metal element, e.g. metal oxides, metal oxynitrides or metal oxycarbides characterised by the metal
- H10P14/69394—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses the material containing at least one metal element, e.g. metal oxides, metal oxynitrides or metal oxycarbides characterised by the metal the material containing titanium, e.g. TiO2
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W20/00—Interconnections in chips, wafers or substrates
- H10W20/01—Manufacture or treatment
- H10W20/031—Manufacture or treatment of conductive parts of the interconnections
- H10W20/064—Manufacture or treatment of conductive parts of the interconnections by modifying the conductivity of conductive parts, e.g. by alloying
- H10W20/066—Manufacture or treatment of conductive parts of the interconnections by modifying the conductivity of conductive parts, e.g. by alloying by forming silicides of refractory metals
Landscapes
- Electrodes Of Semiconductors (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60112606A JPS61270870A (ja) | 1985-05-25 | 1985-05-25 | 半導体装置 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| DE3614793A1 true DE3614793A1 (de) | 1986-11-27 |
| DE3614793C2 DE3614793C2 (https=) | 1989-01-26 |
Family
ID=14590935
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| DE19863614793 Granted DE3614793A1 (de) | 1985-05-25 | 1986-05-02 | Halbleiterbauelement und dessen herstellung |
Country Status (3)
| Country | Link |
|---|---|
| JP (1) | JPS61270870A (https=) |
| KR (1) | KR890004464B1 (https=) |
| DE (1) | DE3614793A1 (https=) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE3807788A1 (de) * | 1987-03-10 | 1988-09-22 | Mitsubishi Electric Corp | Verfahren zum herstellen einer halbleitereinrichtung |
| DE4118380A1 (de) * | 1991-01-31 | 1992-08-13 | Samsung Electronics Co Ltd | Verfahren zur bildung von metalleitungen an halbleiterbauelementen |
| US5229325A (en) * | 1991-01-31 | 1993-07-20 | Samsung Electronics Co., Ltd. | Method for forming metal wirings of semiconductor device |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5034348A (en) * | 1990-08-16 | 1991-07-23 | International Business Machines Corp. | Process for forming refractory metal silicide layers of different thicknesses in an integrated circuit |
| JP2940880B2 (ja) * | 1990-10-09 | 1999-08-25 | 三菱電機株式会社 | 半導体装置およびその製造方法 |
| KR102064865B1 (ko) * | 2011-06-08 | 2020-01-10 | 가부시키가이샤 한도오따이 에네루기 켄큐쇼 | 스퍼터링 타겟, 스퍼터링 타겟의 제조 방법 및 박막의 형성 방법 |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4228212A (en) * | 1979-06-11 | 1980-10-14 | General Electric Company | Composite conductive structures in integrated circuits |
| EP0110211A2 (en) * | 1982-12-02 | 1984-06-13 | International Business Machines Corporation | Bipolar transistor integrated circuit and method for manufacturing |
| EP0157052A1 (en) * | 1984-03-16 | 1985-10-09 | Genus, Inc. | Low resistivity tungsten silicon composite film |
-
1985
- 1985-05-25 JP JP60112606A patent/JPS61270870A/ja active Pending
- 1985-11-04 KR KR1019850008215A patent/KR890004464B1/ko not_active Expired
-
1986
- 1986-05-02 DE DE19863614793 patent/DE3614793A1/de active Granted
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4228212A (en) * | 1979-06-11 | 1980-10-14 | General Electric Company | Composite conductive structures in integrated circuits |
| EP0110211A2 (en) * | 1982-12-02 | 1984-06-13 | International Business Machines Corporation | Bipolar transistor integrated circuit and method for manufacturing |
| EP0157052A1 (en) * | 1984-03-16 | 1985-10-09 | Genus, Inc. | Low resistivity tungsten silicon composite film |
Non-Patent Citations (13)
| Title |
|---|
| 1984, S. 209 - 211 * |
| US-Z: Appl. Phys. Lett.43, 8.Okt.1984, S.905-907 |
| US-Z: Appl.Phys.Lett.,Bd.36,1980,S.456-458 * |
| US-Z: IBM Techn.Disc.Bull.,Vol.25,Nr.12, Mai 1983,S.6398-6399 * |
| US-Z: Solid State Technology,Jan.1981, S.65 - 72, 92 * |
| US-Z:Appl.Phys.Lett.42,1983,S.361-363 * |
| US-Z:IBM Techn.Dicsl.Bull., Bd.24, 1982,S.6272 * |
| US-Z:IEEE Electron Device Letters,Bd.EDL-5, 1984, S.166 - 168 * |
| US-Z:IEEE Transactions on Electron Devices, Vol. ED-32,Nr.2,Febr.1985,S.141 - 149 * |
| US-Z:Solid State Technology, März 1983, S.125 - 128 * |
| Vol.25, Nr.4, Sept.1982, S.1920-1921 |
| Vol.25,Nr.3A,Aug.1982,S.1177-1178 * |
| Vol.25,Nr.4, Sept.1982,S.1920-1921, US-Z:Appl.Phys.Lett.43,8,Okt.1984,S.905-907 * |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE3807788A1 (de) * | 1987-03-10 | 1988-09-22 | Mitsubishi Electric Corp | Verfahren zum herstellen einer halbleitereinrichtung |
| DE4118380A1 (de) * | 1991-01-31 | 1992-08-13 | Samsung Electronics Co Ltd | Verfahren zur bildung von metalleitungen an halbleiterbauelementen |
| US5229325A (en) * | 1991-01-31 | 1993-07-20 | Samsung Electronics Co., Ltd. | Method for forming metal wirings of semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| KR890004464B1 (ko) | 1989-11-04 |
| DE3614793C2 (https=) | 1989-01-26 |
| JPS61270870A (ja) | 1986-12-01 |
| KR860009497A (ko) | 1986-12-23 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| OM8 | Search report available as to paragraph 43 lit. 1 sentence 1 patent law | ||
| 8110 | Request for examination paragraph 44 | ||
| D2 | Grant after examination | ||
| 8364 | No opposition during term of opposition | ||
| 8320 | Willingness to grant licences declared (paragraph 23) | ||
| 8328 | Change in the person/name/address of the agent |
Representative=s name: PRUFER & PARTNER GBR, 81545 MUENCHEN |