DE4022398C2 - - Google Patents

Info

Publication number
DE4022398C2
DE4022398C2 DE4022398A DE4022398A DE4022398C2 DE 4022398 C2 DE4022398 C2 DE 4022398C2 DE 4022398 A DE4022398 A DE 4022398A DE 4022398 A DE4022398 A DE 4022398A DE 4022398 C2 DE4022398 C2 DE 4022398C2
Authority
DE
Germany
Prior art keywords
film
titanium silicide
titanium
silicide film
layer structure
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE4022398A
Other languages
German (de)
English (en)
Other versions
DE4022398A1 (de
Inventor
Akihiko Itami Hyogo Jp Ohsaki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Publication of DE4022398A1 publication Critical patent/DE4022398A1/de
Application granted granted Critical
Publication of DE4022398C2 publication Critical patent/DE4022398C2/de
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/064—Manufacture or treatment of conductive parts of the interconnections by modifying the conductivity of conductive parts, e.g. by alloying
    • H10W20/066—Manufacture or treatment of conductive parts of the interconnections by modifying the conductivity of conductive parts, e.g. by alloying by forming silicides of refractory metals
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/31—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D1/00—Resistors, capacitors or inductors
    • H10D1/60—Capacitors
    • H10D1/62—Capacitors having potential barriers
    • H10D1/66—Conductor-insulator-semiconductor capacitors, e.g. MOS capacitors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0212—Manufacture or treatment of FETs having insulated gates [IGFET] using self-aligned silicidation
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0223—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate
    • H10D30/0227—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate having both lightly-doped source and drain extensions and source and drain regions self-aligned to the sides of the gate, e.g. lightly-doped drain [LDD] MOSFET or double-diffused drain [DDD] MOSFET
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/011—Manufacture or treatment of electrodes ohmically coupled to a semiconductor
    • H10D64/0111—Manufacture or treatment of electrodes ohmically coupled to a semiconductor to Group IV semiconductors
    • H10D64/0112—Manufacture or treatment of electrodes ohmically coupled to a semiconductor to Group IV semiconductors using conductive layers comprising silicides
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/013—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator
    • H10D64/01302—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H10D64/01304—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H10D64/01306—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon
    • H10D64/01308—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon the conductor further comprising a non-elemental silicon additional conductive layer, e.g. a metal silicide layer formed by the reaction of silicon with an implanted metal
    • H10D64/0131—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon the conductor further comprising a non-elemental silicon additional conductive layer, e.g. a metal silicide layer formed by the reaction of silicon with an implanted metal the additional conductive layer comprising a silicide layer formed by the silicidation reaction between the layer of silicon with a metal layer which is not formed by metal implantation
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/23—Electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. sources, drains, anodes or cathodes
    • H10D64/251—Source or drain electrodes for field-effect devices
    • H10D64/258—Source or drain electrodes for field-effect devices characterised by the relative positions of the source or drain electrodes with respect to the gate electrode
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/23—Electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. sources, drains, anodes or cathodes
    • H10D64/251—Source or drain electrodes for field-effect devices
    • H10D64/258—Source or drain electrodes for field-effect devices characterised by the relative positions of the source or drain electrodes with respect to the gate electrode
    • H10D64/259—Source or drain electrodes being self-aligned with the gate electrode and having bottom surfaces higher than the interface between the channel and the gate dielectric
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
    • H10D64/661—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon having vertical doping variation
    • H10D64/662—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon having vertical doping variation the conductor further comprising additional layers, e.g. multiple silicon layers having different crystal structures
    • H10D64/663—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon having vertical doping variation the conductor further comprising additional layers, e.g. multiple silicon layers having different crystal structures the additional layers comprising a silicide layer contacting the layer of silicon, e.g. polycide gates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/63—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the formation processes
    • H10P14/6302—Non-deposition formation processes
    • H10P14/6304—Formation by oxidation, e.g. oxidation of the substrate
    • H10P14/6306—Formation by oxidation, e.g. oxidation of the substrate of the semiconductor materials
    • H10P14/6308—Formation by oxidation, e.g. oxidation of the substrate of the semiconductor materials of Group IV semiconductors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P32/00—Diffusion of dopants within, into or out of wafers, substrates or parts of devices
    • H10P32/10—Diffusion of dopants within, into or out of semiconductor bodies or layers
    • H10P32/14—Diffusion of dopants within, into or out of semiconductor bodies or layers within a single semiconductor body or layer in a solid phase; between different semiconductor bodies or layers, both in a solid phase
    • H10P32/1408—Diffusion of dopants within, into or out of semiconductor bodies or layers within a single semiconductor body or layer in a solid phase; between different semiconductor bodies or layers, both in a solid phase from or through or into an external applied layer, e.g. photoresist or nitride layers
    • H10P32/1414—Diffusion of dopants within, into or out of semiconductor bodies or layers within a single semiconductor body or layer in a solid phase; between different semiconductor bodies or layers, both in a solid phase from or through or into an external applied layer, e.g. photoresist or nitride layers the applied layer being silicon, silicide or SIPOS, e.g. polysilicon or porous silicon
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P32/00—Diffusion of dopants within, into or out of wafers, substrates or parts of devices
    • H10P32/10—Diffusion of dopants within, into or out of semiconductor bodies or layers
    • H10P32/17—Diffusion of dopants within, into or out of semiconductor bodies or layers characterised by the semiconductor material
    • H10P32/171—Diffusion of dopants within, into or out of semiconductor bodies or layers characterised by the semiconductor material being group IV material
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/44—Conductive materials thereof
    • H10W20/4403—Conductive materials thereof based on metals, e.g. alloys, metal silicides
    • H10W20/4437—Conductive materials thereof based on metals, e.g. alloys, metal silicides the principal metal being a transition metal
    • H10W20/4441—Conductive materials thereof based on metals, e.g. alloys, metal silicides the principal metal being a transition metal the principal metal being a refractory metal

Landscapes

  • Electrodes Of Semiconductors (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
DE4022398A 1989-07-14 1990-07-13 Thermisch stabiles titan-silicid und verfahren zu dessen herstellung Granted DE4022398A1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1183221A JPH0758773B2 (ja) 1989-07-14 1989-07-14 半導体装置の製造方法及び半導体装置

Publications (2)

Publication Number Publication Date
DE4022398A1 DE4022398A1 (de) 1991-01-24
DE4022398C2 true DE4022398C2 (https=) 1993-09-02

Family

ID=16131911

Family Applications (1)

Application Number Title Priority Date Filing Date
DE4022398A Granted DE4022398A1 (de) 1989-07-14 1990-07-13 Thermisch stabiles titan-silicid und verfahren zu dessen herstellung

Country Status (3)

Country Link
US (1) US6198143B1 (https=)
JP (1) JPH0758773B2 (https=)
DE (1) DE4022398A1 (https=)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10056866A1 (de) * 2000-11-16 2002-06-13 Advanced Micro Devices Inc Verfahren zur Bildung einer Ätzstoppschicht während der Herstellung eines Halbleiterbauteils

Families Citing this family (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0517288B1 (en) * 1991-04-29 1996-04-10 Koninklijke Philips Electronics N.V. Diffusion barrier enhancement in metallization structure for semiconductor device fabrication
JP2611726B2 (ja) * 1993-10-07 1997-05-21 日本電気株式会社 半導体装置の製造方法
JP2699845B2 (ja) * 1993-12-22 1998-01-19 日本電気株式会社 半導体装置の製造方法
US6200871B1 (en) * 1994-08-30 2001-03-13 Texas Instruments Incorporated High performance self-aligned silicide process for sub-half-micron semiconductor technologies
TW374196B (en) * 1996-02-23 1999-11-11 Semiconductor Energy Lab Co Ltd Semiconductor thin film and method for manufacturing the same and semiconductor device and method for manufacturing the same
US6028002A (en) * 1996-05-15 2000-02-22 Micron Technology, Inc. Refractory metal roughness reduction using high temperature anneal in hydrides or organo-silane ambients
FR2760563A1 (fr) * 1997-03-07 1998-09-11 Sgs Thomson Microelectronics Pseudofusible et application a un circuit d'etablissement d'une bascule a la mise sous tension
US6348411B1 (en) 1998-09-03 2002-02-19 Micron Technology, Inc. Method of making a contact structure
KR100304962B1 (ko) * 1998-11-24 2001-10-20 김영환 텅스텐비트라인형성방법
JP3472738B2 (ja) * 1999-12-24 2003-12-02 Ｎｅｃエレクトロニクス株式会社 回路製造方法、半導体装置
JP2002043564A (ja) * 2000-07-21 2002-02-08 Mitsubishi Electric Corp サリサイドトランジスタの製造方法、半導体記憶装置および半導体装置
US20030168730A1 (en) * 2002-03-08 2003-09-11 Howard Davidson Carbon foam heat exchanger for integrated circuit
US20090267157A1 (en) * 2004-12-06 2009-10-29 Koninklijke Philips Electronics N.V. Method or manufacturing a semiconductor device and semiconductor device obtained by using such a method
US7485934B2 (en) * 2005-10-25 2009-02-03 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated semiconductor structure for SRAM cells
JP5022614B2 (ja) * 2006-03-20 2012-09-12 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
JP5653577B2 (ja) * 2007-08-31 2015-01-14 アイメックＩｍｅｃ ゲルマナイド成長の改良方法およびそれにより得られたデバイス
JP2011176348A (ja) * 2011-04-25 2011-09-08 Renesas Electronics Corp 半導体装置
FR2990295B1 (fr) * 2012-05-04 2016-11-25 St Microelectronics Sa Procede de formation de contacts de grille, de source et de drain sur un transistor mos
US9469107B2 (en) 2013-07-12 2016-10-18 Hewlett-Packard Development Company, L.P. Thermal inkjet printhead stack with amorphous metal resistor
WO2015005933A1 (en) 2013-07-12 2015-01-15 Hewlett-Packard Development Company, L.P. Thermal inkjet printhead stack with amorphous thin metal protective layer
WO2016018284A1 (en) 2014-07-30 2016-02-04 Hewlett-Packard Development Company, L.P. Amorphous metal alloy electrodes in non-volatile device applications

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4276557A (en) * 1978-12-29 1981-06-30 Bell Telephone Laboratories, Incorporated Integrated semiconductor circuit structure and method for making it
JPS62113421A (ja) * 1985-11-13 1987-05-25 Toshiba Corp 半導体装置の製造方法
JPS6390126A (ja) * 1986-10-03 1988-04-21 Hitachi Ltd 半導体電極の形成方法
US4905073A (en) * 1987-06-22 1990-02-27 At&T Bell Laboratories Integrated circuit with improved tub tie
JPS644069A (en) * 1987-06-26 1989-01-09 Oki Electric Ind Co Ltd Manufacture of semiconductor device
US4818715A (en) * 1987-07-09 1989-04-04 Industrial Technology Research Institute Method of fabricating a LDDFET with self-aligned silicide
US4907048A (en) * 1987-11-23 1990-03-06 Xerox Corporation Double implanted LDD transistor self-aligned with gate
US4949136A (en) * 1988-06-09 1990-08-14 University Of Connecticut Submicron lightly doped field effect transistors
US4859278A (en) * 1988-08-11 1989-08-22 Xerox Corporation Fabrication of high resistive loads utilizing a single level polycide process
JPH0258874A (ja) * 1988-08-24 1990-02-28 Nec Corp 半導体集積回路装置

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10056866A1 (de) * 2000-11-16 2002-06-13 Advanced Micro Devices Inc Verfahren zur Bildung einer Ätzstoppschicht während der Herstellung eines Halbleiterbauteils
DE10056866C2 (de) * 2000-11-16 2002-10-24 Advanced Micro Devices Inc Verfahren zur Bildung einer Ätzstoppschicht während der Herstellung eines Halbleiterbauteils

Also Published As

Publication number Publication date
JPH0346323A (ja) 1991-02-27
US6198143B1 (en) 2001-03-06
DE4022398A1 (de) 1991-01-24
JPH0758773B2 (ja) 1995-06-21

Similar Documents

Publication Publication Date Title
DE4022398C2 (https=)
DE19829300B4 (de) Ferroelektrische Speichereinrichtung mit elektrischer Verbindung zwischen einer unteren Kondensatorelektrode und einem Kontaktstopfen sowie Verfahren zu deren Herstellung
DE19950708C2 (de) Verfahren zum Bilden von selbstjustierenden Cobaltsilicid-Schichten mit lokal unterschiedlicher Schichtdicke
DE3311635C2 (https=)
DE69332136T2 (de) Halbleiterbauelement mit einem Kontakt und Verfahren zu seiner Herstellung
DE4010618C2 (de) Verfahren zur Herstellung einer Halbleitervorrichtung
DE10014315B4 (de) Verfahren zum Herstellen eines Halbleiterspeichers
DE3334333A1 (de) Verfahren zur herstellung eines mos-einrichtung mit selbstjustierten kontakten
DE69526486T2 (de) Verfahren zum Herstellen einer Kontaktfläche in einer integrierten Schaltung
DE3122437A1 (de) Verfahren zum herstellen eines mos-bauelements
DE19524027C2 (de) Halbleitervorrichtung und zugeordnetes Herstellungsverfahren
DE69420805T2 (de) Herstellungsverfahren für Kontakte in dem Speichergebiet und dem Randgebiet eines IC
DE3931127C2 (de) Verfahren zum Herstellen einer Halbleitereinrichtung
DE10208904B4 (de) Verfahren zur Herstellung unterschiedlicher Silicidbereiche auf verschiedenen Silicium enthaltenden Gebieten in einem Halbleiterelement
DE4244115C2 (de) Halbleitervorrichtung und Verfahren zum Herstellen der Halbleitervorrichtung
DE10056866C2 (de) Verfahren zur Bildung einer Ätzstoppschicht während der Herstellung eines Halbleiterbauteils
DE4122712A1 (de) Halbleitervorrichtung
DE10156442A1 (de) Halbleitervorrichtung
DE10238774A1 (de) Halbleitervorrichtung
DE3650170T2 (de) Halbleiteranordnung mit Verbindungselektroden.
DE3000121A1 (de) Verfahren zur herstellung einer mos-halbleitereinrichtung mit selbstjustierten anschluessen
DE4411851A1 (de) Halbleitervorrichtung mit Grabenisolationsstruktur und Herstellungsverfahren dafür
DE69207442T2 (de) Verfahren zum Herstellen von integrierten Schaltstrukturen
DE3614793C2 (https=)
DE4443593C2 (de) Halbleitervorrichtung und Verfahren zu deren Herstellung

Legal Events

Date Code Title Description
OP8 Request for examination as to paragraph 44 patent law
D2 Grant after examination
8364 No opposition during term of opposition
8320 Willingness to grant licences declared (paragraph 23)
8339 Ceased/non-payment of the annual fee