KR860009497A - 반도체 장치 - Google Patents

반도체 장치 Download PDF

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KR860009497A
KR860009497A KR1019850008215A KR850008215A KR860009497A KR 860009497 A KR860009497 A KR 860009497A KR 1019850008215 A KR1019850008215 A KR 1019850008215A KR 850008215 A KR850008215 A KR 850008215A KR 860009497 A KR860009497 A KR 860009497A
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film
electric
semiconductor device
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KR1019850008215A
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KR890004464B1 (ko
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모도 다쓰 오 오까
즈 마사 히로 시미
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시기 모리야
미쓰비시 덴기 가부시끼 가이샤
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    • HELECTRICITY
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    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
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    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
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    • H01L21/02321Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment introduction of substances into an already existing insulating layer
    • H01L21/02323Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment introduction of substances into an already existing insulating layer introduction of oxygen
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    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
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    • H01L21/02109Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
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    • H01L21/02172Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
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    • H01L21/02186Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal the material containing titanium, e.g. TiO2
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    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76886Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances
    • H01L21/76889Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances by forming silicides of refractory metals
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    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
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    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
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    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
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    • H01L29/4925Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement
    • H01L29/4933Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement with a silicide layer contacting the silicon layer, e.g. Polycide gate
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    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
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    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

내용 없음

Description

반도체 장치
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 본 발명 실시예의 반도체 장치를 표시한 단면도.
제2도 (a)∼(h)는 본 발명 실시예의 반도체 장치의 제조 방법의 주요 공정 단계에서의 상태를 표시한 단면도.
* 도면의 주요부분에 대한 부호의 설명
1 : 실리콘 기판 2 : 두꺼운 절연막
3, 30 : 얇은 절연막 4, 40 : 다결정 실리콘막
5a, 5b : 측벽 6 : 티타늄
7a, 7b, 7c : 티타늄 실리사이드막 8 : 질화 티탄막
9a, 9b, 15a, 15b : 불순물확산층 10, 10a, 10b, 10c : 산화 티타늄막
11, 11a, 11b, 11c : 층간 절연막 12a, 12b : 접촉구멍
13a, 13b : 알루미늄 합금막 14 : 최저치 전압 제어용 불순물층
(각 도면중 동일부호는 동일 또는 상당 부분을 표시한 것임)

Claims (10)

  1. MOS 형 전계효과 트랜지스터이며 반도체 실리콘 기판과 전기 반도체 실리콘 기판상에 형성되며 소스·드레인 영역이 되는 불순물 확산층과 전기 반도체 실리콘 기판 상에 형성되는 게이트 절연막과 전기 게이트 절연막상에 형성되며 다결정 실리콘으로 된 게이트 전극과 전기 게이트 전극의 측부에 당해 게이트 전극 및 전기 불순물 확산층에 접촉하여 형성되며 당해 게이트 전극과 당해 불순물 확산층과를 절연하는 절연막과 전기 불순물 확산층상 및 전기 게이트 전극상에 형성되는 금속 실리사이드막과 전기 금속 실리사이드 막상 및 전기 절연막상에 형성되는 금속 산화막과 전기 금속 산화막상에 형성되는 층간 절연막과를 구비한 반도체 장치.
  2. 제 1 항에 있어서 전기 층간 절연막 및 전기 금속산화막을 관통하는 접촉구멍이 설치되며 전기 접촉구멍에는 전기 실리사이드막과 전기적으로 접속하는 배선용 층막이 형성되는 반도체 장치.
  3. 제 1 항에 있어서 전기 금속 실리사이드 막은 Ti, V, Zr, Nb, Hf, Ta 로 된 군에서 임의로 선택된 1물질의 실리사이드막으로 된 반도체 장치.
  4. 제 1 항에 있어서 전기 금속 산화막은 Ti, V, Zr, Nb, Hf, Ta 로 된 군에서 임의로 선택된 1물질의 산화막으로 된 반도체 장치.
  5. 제 2 항에 있어서 전기 배선용막은 MO 막으로 된 반도체 장치.
  6. 제 2 항에 있어서 전기 배선용막은 W 막으로 된 반도체 장치.
  7. 제 2 항에 있어서 전기 배선용막은 MO, W, Ta, Ti, V, Zr, Nb, Hf, Cr 로 된 군에서 임의로 선택된 1물질의 실리사이드막으로 된 반도체 장치.
  8. 제 2 항에 있어서 전기 배선용막은 MO, W, Ta, Ti, V, Zr, Nb, Hf, Cr 로 된 군에서 임의로 선택된 3물질의 실리사이드막으로 된 반도체 장치.
  9. 제 2 항에 있어서 전기 배선용막은 TiW, TiN, TaN, Al 합금의 군에서 임의로 선택된 1물질의 막으로 된 반도체 장치.
  10. 제 2 항에 있어서 전기 배선용막은 MO막, W막, MO, W, Ta, Ti, V, Zr, Nb, Hf, Cr 로 된 군에서 임의로 선택된 1물질의 실리사이드막, MO, W, Ta, Ti, V, Zr, Nb, Hf, Cr 로 된 군에서 임의로 선택된 3물질의 실리사이드막 및 TiW, TiN, TaN, Al 합금의 군에서 임의로 선택된 1물질의 막의 임의의 조합으로 된 다막층의 반도체 장치.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019850008215A 1985-05-25 1985-11-04 반도체 장치 KR890004464B1 (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP60112606A JPS61270870A (ja) 1985-05-25 1985-05-25 半導体装置
JP60-112606 1985-05-25
JP112606 1985-05-25

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KR860009497A true KR860009497A (ko) 1986-12-23
KR890004464B1 KR890004464B1 (ko) 1989-11-04

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DE (1) DE3614793A1 (ko)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63221647A (ja) * 1987-03-10 1988-09-14 Mitsubishi Electric Corp 半導体装置の製造方法
US5034348A (en) * 1990-08-16 1991-07-23 International Business Machines Corp. Process for forming refractory metal silicide layers of different thicknesses in an integrated circuit
JP2940880B2 (ja) * 1990-10-09 1999-08-25 三菱電機株式会社 半導体装置およびその製造方法
KR930006128B1 (ko) * 1991-01-31 1993-07-07 삼성전자 주식회사 반도체장치의 금속 배선 형성방법
US5229325A (en) * 1991-01-31 1993-07-20 Samsung Electronics Co., Ltd. Method for forming metal wirings of semiconductor device

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4228212A (en) * 1979-06-11 1980-10-14 General Electric Company Composite conductive structures in integrated circuits
US4521952A (en) * 1982-12-02 1985-06-11 International Business Machines Corporation Method of making integrated circuits using metal silicide contacts
US4629635A (en) * 1984-03-16 1986-12-16 Genus, Inc. Process for depositing a low resistivity tungsten silicon composite film on a substrate

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DE3614793C2 (ko) 1989-01-26
KR890004464B1 (ko) 1989-11-04
DE3614793A1 (de) 1986-11-27
JPS61270870A (ja) 1986-12-01

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