KR890004464B1 - 반도체 장치 - Google Patents
반도체 장치 Download PDFInfo
- Publication number
- KR890004464B1 KR890004464B1 KR1019850008215A KR850008215A KR890004464B1 KR 890004464 B1 KR890004464 B1 KR 890004464B1 KR 1019850008215 A KR1019850008215 A KR 1019850008215A KR 850008215 A KR850008215 A KR 850008215A KR 890004464 B1 KR890004464 B1 KR 890004464B1
- Authority
- KR
- South Korea
- Prior art keywords
- film
- semiconductor device
- insulating film
- silicide
- electric
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Images
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P95/00—Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
- H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
- H10P14/65—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by treatments performed before or after the formation of the materials
- H10P14/6516—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by treatments performed before or after the formation of the materials of treatments performed after formation of the materials
- H10P14/6518—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by treatments performed before or after the formation of the materials of treatments performed after formation of the materials by introduction of substances into an already-existing insulating layer
- H10P14/6519—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by treatments performed before or after the formation of the materials of treatments performed after formation of the materials by introduction of substances into an already-existing insulating layer the substance being oxygen
- H10P14/6522—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by treatments performed before or after the formation of the materials of treatments performed after formation of the materials by introduction of substances into an already-existing insulating layer the substance being oxygen introduced into a nitride material, e.g. changing SiN to SiON
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/01—Manufacture or treatment
- H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
- H10D30/0223—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
- H10D62/83—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D64/00—Electrodes of devices having potential barriers
- H10D64/60—Electrodes characterised by their materials
- H10D64/62—Electrodes ohmically coupled to a semiconductor
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D64/00—Electrodes of devices having potential barriers
- H10D64/60—Electrodes characterised by their materials
- H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
- H10D64/661—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon having vertical doping variation
- H10D64/662—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon having vertical doping variation the conductor further comprising additional layers, e.g. multiple silicon layers having different crystal structures
- H10D64/663—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon having vertical doping variation the conductor further comprising additional layers, e.g. multiple silicon layers having different crystal structures the additional layers comprising a silicide layer contacting the layer of silicon, e.g. polycide gates
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
- H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
- H10P14/69—Inorganic materials
- H10P14/692—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses
- H10P14/6938—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses the material containing at least one metal element, e.g. metal oxides, metal oxynitrides or metal oxycarbides
- H10P14/6939—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses the material containing at least one metal element, e.g. metal oxides, metal oxynitrides or metal oxycarbides characterised by the metal
- H10P14/69394—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses the material containing at least one metal element, e.g. metal oxides, metal oxynitrides or metal oxycarbides characterised by the metal the material containing titanium, e.g. TiO2
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W20/00—Interconnections in chips, wafers or substrates
- H10W20/01—Manufacture or treatment
- H10W20/031—Manufacture or treatment of conductive parts of the interconnections
- H10W20/064—Manufacture or treatment of conductive parts of the interconnections by modifying the conductivity of conductive parts, e.g. by alloying
- H10W20/066—Manufacture or treatment of conductive parts of the interconnections by modifying the conductivity of conductive parts, e.g. by alloying by forming silicides of refractory metals
Landscapes
- Electrodes Of Semiconductors (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60112606A JPS61270870A (ja) | 1985-05-25 | 1985-05-25 | 半導体装置 |
| JP112606 | 1985-05-25 | ||
| JP60-112606 | 1985-05-25 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR860009497A KR860009497A (ko) | 1986-12-23 |
| KR890004464B1 true KR890004464B1 (ko) | 1989-11-04 |
Family
ID=14590935
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019850008215A Expired KR890004464B1 (ko) | 1985-05-25 | 1985-11-04 | 반도체 장치 |
Country Status (3)
| Country | Link |
|---|---|
| JP (1) | JPS61270870A (https=) |
| KR (1) | KR890004464B1 (https=) |
| DE (1) | DE3614793A1 (https=) |
Families Citing this family (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63221647A (ja) * | 1987-03-10 | 1988-09-14 | Mitsubishi Electric Corp | 半導体装置の製造方法 |
| US5034348A (en) * | 1990-08-16 | 1991-07-23 | International Business Machines Corp. | Process for forming refractory metal silicide layers of different thicknesses in an integrated circuit |
| JP2940880B2 (ja) * | 1990-10-09 | 1999-08-25 | 三菱電機株式会社 | 半導体装置およびその製造方法 |
| US5229325A (en) * | 1991-01-31 | 1993-07-20 | Samsung Electronics Co., Ltd. | Method for forming metal wirings of semiconductor device |
| KR930006128B1 (ko) * | 1991-01-31 | 1993-07-07 | 삼성전자 주식회사 | 반도체장치의 금속 배선 형성방법 |
| KR102064865B1 (ko) * | 2011-06-08 | 2020-01-10 | 가부시키가이샤 한도오따이 에네루기 켄큐쇼 | 스퍼터링 타겟, 스퍼터링 타겟의 제조 방법 및 박막의 형성 방법 |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4228212A (en) * | 1979-06-11 | 1980-10-14 | General Electric Company | Composite conductive structures in integrated circuits |
| US4521952A (en) * | 1982-12-02 | 1985-06-11 | International Business Machines Corporation | Method of making integrated circuits using metal silicide contacts |
| US4629635A (en) * | 1984-03-16 | 1986-12-16 | Genus, Inc. | Process for depositing a low resistivity tungsten silicon composite film on a substrate |
-
1985
- 1985-05-25 JP JP60112606A patent/JPS61270870A/ja active Pending
- 1985-11-04 KR KR1019850008215A patent/KR890004464B1/ko not_active Expired
-
1986
- 1986-05-02 DE DE19863614793 patent/DE3614793A1/de active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| DE3614793A1 (de) | 1986-11-27 |
| DE3614793C2 (https=) | 1989-01-26 |
| JPS61270870A (ja) | 1986-12-01 |
| KR860009497A (ko) | 1986-12-23 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US6696332B2 (en) | Bilayer deposition to avoid unwanted interfacial reactions during high K gate dielectric processing | |
| US5389575A (en) | Self-aligned contact diffusion barrier method | |
| US6013569A (en) | One step salicide process without bridging | |
| US7682968B2 (en) | Self-aligned metal to form contacts to Ge containing substrates and structure formed thereby | |
| JP2005019943A (ja) | ニッケル合金サリサイド工程、それを用いて半導体素子を製造する方法、これにより形成されたニッケル合金シリサイド膜及びそれを用いて製造された半導体素子 | |
| JPH02273934A (ja) | 半導体素子およびその製造方法 | |
| US6461951B1 (en) | Method of forming a sidewall spacer to prevent gouging of device junctions during interlayer dielectric etching including silicide growth over gate spacers | |
| US5194405A (en) | Method of manufacturing a semiconductor device having a silicide layer | |
| US6528402B2 (en) | Dual salicidation process | |
| JPH06151736A (ja) | 半導体集積回路装置及びその製造方法 | |
| KR890004464B1 (ko) | 반도체 장치 | |
| JPH11261063A (ja) | 半導体装置の製造方法 | |
| US6524939B2 (en) | Dual salicidation process | |
| US4935376A (en) | Making silicide gate level runners | |
| US7109116B1 (en) | Method for reducing dendrite formation in nickel silicon salicide processes | |
| KR100819685B1 (ko) | 반도체소자의 제조방법 | |
| GB2177255A (en) | VLSI MOSFET circuits using refractory metal and/or refractory metal silicide | |
| EP0407202A2 (en) | Manufacturing semiconductor devices | |
| KR100365409B1 (ko) | 반도체 소자의 게이트 전극 형성방법 | |
| JP2900897B2 (ja) | 半導体装置の製造方法 | |
| KR940004419B1 (ko) | Mos형 반도체장치 및 그 제조방법 | |
| JPH01106468A (ja) | 半導体装置およびその製造方法 | |
| JPH09186104A (ja) | 半導体装置の製造方法 | |
| JPH07273321A (ja) | 半導体装置およびその製造方法 | |
| JPH0758789B2 (ja) | 半導体装置の製造方法 |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A201 | Request for examination | ||
| PA0109 | Patent application |
St.27 status event code: A-0-1-A10-A12-nap-PA0109 |
|
| PA0201 | Request for examination |
St.27 status event code: A-1-2-D10-D11-exm-PA0201 |
|
| R17-X000 | Change to representative recorded |
St.27 status event code: A-3-3-R10-R17-oth-X000 |
|
| PG1501 | Laying open of application |
St.27 status event code: A-1-1-Q10-Q12-nap-PG1501 |
|
| G160 | Decision to publish patent application | ||
| PG1605 | Publication of application before grant of patent |
St.27 status event code: A-2-2-Q10-Q13-nap-PG1605 |
|
| E701 | Decision to grant or registration of patent right | ||
| PE0701 | Decision of registration |
St.27 status event code: A-1-2-D10-D22-exm-PE0701 |
|
| GRNT | Written decision to grant | ||
| PR0701 | Registration of establishment |
St.27 status event code: A-2-4-F10-F11-exm-PR0701 |
|
| PR1002 | Payment of registration fee |
St.27 status event code: A-2-2-U10-U11-oth-PR1002 Fee payment year number: 1 |
|
| PR1001 | Payment of annual fee |
St.27 status event code: A-4-4-U10-U11-oth-PR1001 Fee payment year number: 4 |
|
| PR1001 | Payment of annual fee |
St.27 status event code: A-4-4-U10-U11-oth-PR1001 Fee payment year number: 5 |
|
| PR1001 | Payment of annual fee |
St.27 status event code: A-4-4-U10-U11-oth-PR1001 Fee payment year number: 6 |
|
| PR1001 | Payment of annual fee |
St.27 status event code: A-4-4-U10-U11-oth-PR1001 Fee payment year number: 7 |
|
| PR1001 | Payment of annual fee |
St.27 status event code: A-4-4-U10-U11-oth-PR1001 Fee payment year number: 8 |
|
| PR1001 | Payment of annual fee |
St.27 status event code: A-4-4-U10-U11-oth-PR1001 Fee payment year number: 9 |
|
| PR1001 | Payment of annual fee |
St.27 status event code: A-4-4-U10-U11-oth-PR1001 Fee payment year number: 10 |
|
| PN2301 | Change of applicant |
St.27 status event code: A-5-5-R10-R13-asn-PN2301 St.27 status event code: A-5-5-R10-R11-asn-PN2301 |
|
| PN2301 | Change of applicant |
St.27 status event code: A-5-5-R10-R13-asn-PN2301 St.27 status event code: A-5-5-R10-R11-asn-PN2301 |
|
| R18-X000 | Changes to party contact information recorded |
St.27 status event code: A-5-5-R10-R18-oth-X000 |
|
| PN2301 | Change of applicant |
St.27 status event code: A-5-5-R10-R13-asn-PN2301 St.27 status event code: A-5-5-R10-R11-asn-PN2301 |
|
| PR1001 | Payment of annual fee |
St.27 status event code: A-4-4-U10-U11-oth-PR1001 Fee payment year number: 11 |
|
| PR1001 | Payment of annual fee |
St.27 status event code: A-4-4-U10-U11-oth-PR1001 Fee payment year number: 12 |
|
| PR1001 | Payment of annual fee |
St.27 status event code: A-4-4-U10-U11-oth-PR1001 Fee payment year number: 13 |
|
| PR1001 | Payment of annual fee |
St.27 status event code: A-4-4-U10-U11-oth-PR1001 Fee payment year number: 14 |
|
| PR1001 | Payment of annual fee |
St.27 status event code: A-4-4-U10-U11-oth-PR1001 Fee payment year number: 15 |
|
| FPAY | Annual fee payment |
Payment date: 20041025 Year of fee payment: 16 |
|
| PR1001 | Payment of annual fee |
St.27 status event code: A-4-4-U10-U11-oth-PR1001 Fee payment year number: 16 |
|
| EXPY | Expiration of term | ||
| PC1801 | Expiration of term |
St.27 status event code: N-4-6-H10-H14-oth-PC1801 Not in force date: 20051105 Ip right cessation event data comment text: Termination Category : EXPIRATION_OF_DURATION |
|
| R18-X000 | Changes to party contact information recorded |
St.27 status event code: A-5-5-R10-R18-oth-X000 |
|
| PN2301 | Change of applicant |
St.27 status event code: A-5-5-R10-R13-asn-PN2301 St.27 status event code: A-5-5-R10-R11-asn-PN2301 |
|
| P22-X000 | Classification modified |
St.27 status event code: A-4-4-P10-P22-nap-X000 |
|
| P22-X000 | Classification modified |
St.27 status event code: A-4-4-P10-P22-nap-X000 |
|
| P22-X000 | Classification modified |
St.27 status event code: A-4-4-P10-P22-nap-X000 |