DE3587744D1 - Steuerlogik für ein Videosystem mit einer Schaltung, welche die Zeilenadresse ausser Kraft setzt. - Google Patents

Steuerlogik für ein Videosystem mit einer Schaltung, welche die Zeilenadresse ausser Kraft setzt.

Info

Publication number
DE3587744D1
DE3587744D1 DE85305225T DE3587744T DE3587744D1 DE 3587744 D1 DE3587744 D1 DE 3587744D1 DE 85305225 T DE85305225 T DE 85305225T DE 3587744 T DE3587744 T DE 3587744T DE 3587744 D1 DE3587744 D1 DE 3587744D1
Authority
DE
Germany
Prior art keywords
overrides
circuit
control logic
row address
video system
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE85305225T
Other languages
English (en)
Other versions
DE3587744T2 (de
Inventor
Jeffrey C Bond
Karl M Guttag
Robert C Thaden
Raymond Pinkham
Mark Novak
Mark W Watts
Jerry Vanaken
John V Moravec
Rudy J Albachten
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Texas Instruments Inc
Original Assignee
Texas Instruments Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US06/633,385 external-priority patent/US4656597A/en
Priority claimed from US06/633,389 external-priority patent/US4654804A/en
Priority claimed from US06/633,383 external-priority patent/US4660156A/en
Priority claimed from US06/633,367 external-priority patent/US4691289A/en
Priority claimed from US06/633,386 external-priority patent/US4656596A/en
Priority claimed from US06/633,388 external-priority patent/US4660155A/en
Priority claimed from US06/633,384 external-priority patent/US4665495A/en
Application filed by Texas Instruments Inc filed Critical Texas Instruments Inc
Publication of DE3587744D1 publication Critical patent/DE3587744D1/de
Application granted granted Critical
Publication of DE3587744T2 publication Critical patent/DE3587744T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/001—Arbitration of resources in a display system, e.g. control of access to frame buffer by video controller and/or main processor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/003—Details of a display terminal, the details relating to the control arrangement of the display terminal and to the interfaces thereto
    • G09G5/005—Adapting incoming signals to the display format of the display terminal
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
    • G09G5/363—Graphics controllers
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
    • G09G5/39—Control of the bit-mapped memory
    • G09G5/391—Resolution modifying circuits, e.g. variable screen formats
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
    • G09G5/39—Control of the bit-mapped memory
    • G09G5/393—Arrangements for updating the contents of the bit-mapped memory
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
    • G09G5/39—Control of the bit-mapped memory
    • G09G5/395—Arrangements specially adapted for transferring the contents of the bit-mapped memory to the screen
    • G09G5/397—Arrangements specially adapted for transferring the contents of two or more bit-mapped memories to the screen simultaneously, e.g. for mixing or overlay
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/06—Details of flat display driving waveforms
    • G09G2310/061—Details of flat display driving waveforms for resetting or blanking
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2360/00—Aspects of the architecture of display systems
    • G09G2360/12—Frame memory handling
    • G09G2360/126—The frame memory having additional data ports, not inclusive of standard details of the output serial port of a VRAM
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2360/00—Aspects of the architecture of display systems
    • G09G2360/12—Frame memory handling
    • G09G2360/128—Frame memory using a Synchronous Dynamic RAM [SDRAM]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2360/00—Aspects of the architecture of display systems
    • G09G2360/18—Use of a frame buffer in a display terminal, inclusive of the display panel
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
    • G09G5/39—Control of the bit-mapped memory
    • G09G5/399—Control of the bit-mapped memory using two or more bit-mapped memories, the operations of which are switched in time, e.g. ping-pong buffers

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Multimedia (AREA)
  • Computer Graphics (AREA)
  • Controls And Circuits For Display Device (AREA)
  • Image Input (AREA)
  • Digital Computer Display Output (AREA)
  • Memory System (AREA)
DE19853587744 1984-07-23 1985-07-23 Steuerlogik für ein Videosystem mit einer Schaltung, welche die Zeilenadresse ausser Kraft setzt. Expired - Fee Related DE3587744T2 (de)

Applications Claiming Priority (8)

Application Number Priority Date Filing Date Title
US63338784A 1984-07-23 1984-07-23
US06/633,389 US4654804A (en) 1984-07-23 1984-07-23 Video system with XY addressing capabilities
US06/633,383 US4660156A (en) 1984-07-23 1984-07-23 Video system with single memory space for instruction, program data and display data
US06/633,367 US4691289A (en) 1984-07-23 1984-07-23 State machine standard cell that supports both a Moore and a Mealy implementation
US06/633,386 US4656596A (en) 1984-07-23 1984-07-23 Video memory controller
US06/633,388 US4660155A (en) 1984-07-23 1984-07-23 Single chip video system with separate clocks for memory controller, CRT controller
US06/633,385 US4656597A (en) 1984-07-23 1984-07-23 Video system controller with a row address override circuit
US06/633,384 US4665495A (en) 1984-07-23 1984-07-23 Single chip dram controller and CRT controller

Publications (2)

Publication Number Publication Date
DE3587744D1 true DE3587744D1 (de) 1994-03-17
DE3587744T2 DE3587744T2 (de) 1994-05-19

Family

ID=27575495

Family Applications (3)

Application Number Title Priority Date Filing Date
DE19853587744 Expired - Fee Related DE3587744T2 (de) 1984-07-23 1985-07-23 Steuerlogik für ein Videosystem mit einer Schaltung, welche die Zeilenadresse ausser Kraft setzt.
DE19853588174 Expired - Fee Related DE3588174T2 (de) 1984-07-23 1985-07-23 Videosystem
DE19853588173 Expired - Fee Related DE3588173T2 (de) 1984-07-23 1985-07-23 Videosystem

Family Applications After (2)

Application Number Title Priority Date Filing Date
DE19853588174 Expired - Fee Related DE3588174T2 (de) 1984-07-23 1985-07-23 Videosystem
DE19853588173 Expired - Fee Related DE3588173T2 (de) 1984-07-23 1985-07-23 Videosystem

Country Status (3)

Country Link
EP (3) EP0482678B1 (de)
JP (2) JPH05281934A (de)
DE (3) DE3587744T2 (de)

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JPS63201791A (ja) * 1987-02-12 1988-08-19 インターナシヨナル・ビジネス・マシーンズ・コーポレーシヨン 処理システム
US4884069A (en) * 1987-03-19 1989-11-28 Apple Computer, Inc. Video apparatus employing VRAMs
ATE84162T1 (de) * 1987-03-20 1993-01-15 Ibm Rechnersystem mit einem videosubsystem.
US5001652A (en) * 1987-03-20 1991-03-19 International Business Machines Corporation Memory arbitration for video subsystems
JP2854867B2 (ja) * 1987-09-14 1999-02-10 ジーディーイー システムズ インコーポレイテッド イメージ処理システム及び画素データ転送法
US5113180A (en) * 1988-04-20 1992-05-12 International Business Machines Corporation Virtual display adapter
JP3068842B2 (ja) * 1990-08-27 2000-07-24 任天堂株式会社 画像処理装置におけるダイレクトメモリアクセス装置およびそれに用いる外部記憶装置
WO1997008676A1 (en) * 1995-08-28 1997-03-06 Cirrus Logic, Inc. Circuits and methods for controlling the refresh of a frame buffer comprising an off-screen area
TW316965B (de) * 1995-10-31 1997-10-01 Cirrus Logic Inc
EP0786756B1 (de) * 1996-01-23 2009-03-25 Hewlett-Packard Company, A Delaware Corporation Arbitrierung für Datenübertragung für ein Anzeigesteuergerät
US6678204B2 (en) * 2001-12-27 2004-01-13 Elpida Memory Inc. Semiconductor memory device with high-speed operation and methods of using and designing thereof
EP2347417B1 (de) * 2008-09-03 2018-04-18 Marvell World Trade Ltd. Programmieren von daten in einem mehrebenen-flash-speicher
US8300056B2 (en) 2008-10-13 2012-10-30 Apple Inc. Seamless display migration
US8797334B2 (en) 2010-01-06 2014-08-05 Apple Inc. Facilitating efficient switching between graphics-processing units
US8368702B2 (en) 2010-01-06 2013-02-05 Apple Inc. Policy-based switching between graphics-processing units
US8648868B2 (en) 2010-01-06 2014-02-11 Apple Inc. Color correction to facilitate switching between graphics-processing units

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US4125873A (en) * 1977-06-29 1978-11-14 International Business Machines Corporation Display compressed image refresh system
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US4288706A (en) 1978-10-20 1981-09-08 Texas Instruments Incorporated Noise immunity in input buffer circuit for semiconductor memory
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JPS5926031B2 (ja) * 1979-03-28 1984-06-23 日本電信電話株式会社 記憶素子
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US4347587A (en) * 1979-11-23 1982-08-31 Texas Instruments Incorporated Semiconductor integrated circuit memory device with both serial and random access arrays
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Also Published As

Publication number Publication date
EP0481534B1 (de) 1998-01-14
DE3588174T2 (de) 1998-06-10
DE3588173T2 (de) 1998-06-10
JPH1091136A (ja) 1998-04-10
DE3587744T2 (de) 1994-05-19
EP0182454A3 (en) 1988-03-23
EP0182454A2 (de) 1986-05-28
EP0481534A2 (de) 1992-04-22
DE3588174D1 (de) 1998-02-19
EP0482678B1 (de) 1998-01-14
EP0482678A3 (en) 1992-09-16
EP0182454B1 (de) 1994-02-02
EP0482678A2 (de) 1992-04-29
DE3588173D1 (de) 1998-02-19
JPH05281934A (ja) 1993-10-29
EP0481534A3 (en) 1992-08-26

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee