ES2036559T3 - Sistema de ordenador con subsistema de video. - Google Patents

Sistema de ordenador con subsistema de video.

Info

Publication number
ES2036559T3
ES2036559T3 ES198787115759T ES87115759T ES2036559T3 ES 2036559 T3 ES2036559 T3 ES 2036559T3 ES 198787115759 T ES198787115759 T ES 198787115759T ES 87115759 T ES87115759 T ES 87115759T ES 2036559 T3 ES2036559 T3 ES 2036559T3
Authority
ES
Spain
Prior art keywords
cpu
video
access
screen
cycles
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
ES198787115759T
Other languages
English (en)
Inventor
Stephen Patrick Thompson
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Application granted granted Critical
Publication of ES2036559T3 publication Critical patent/ES2036559T3/es
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/14—Digital output to display device ; Cooperation and interconnection of the display device with other functional units
    • G06F3/153—Digital output to display device ; Cooperation and interconnection of the display device with other functional units using cathode-ray tubes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/001—Arbitration of resources in a display system, e.g. control of access to frame buffer by video controller and/or main processor

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Multimedia (AREA)
  • Computer Hardware Design (AREA)
  • Human Computer Interaction (AREA)
  • General Engineering & Computer Science (AREA)
  • Controls And Circuits For Display Device (AREA)
  • Digital Computer Display Output (AREA)
  • Bus Control (AREA)

Abstract

UN COMPUTADOR INCLUYE UN SUBSISTEMA DE VIDEO CON UNA PANTALLA CRT, UN CONTROLADOR DE VIDEO Y UNA MEMORIA DE VIDEO PARA DATOS DEL CRT QUE REQUIERE EL ACCESO POR EL CONTROLADOR Y UNA CPU. EL SUBSISTEMA CONTROLA LA ACTIVIDAD DE LA PANTALLA CRT Y EL CONTROLADOR DE VIDEO Y CADA VEZ QUE LA PANTALLA CRT NO SE NECESITA CON INDIFERENCIA DEL TIEMPO DE OCURRENCIA, SE PERMITE QUE LA CPU TENGA ACCESO A LA MEMORIA DE VIDEO DURANTE EL CICLO O CICLOS EN QUE SE PRODUCE DICHA INACTIVIDAD DE LA PANTALLA. SE ASEGURA UN NUMERO MINIMO GARANTIZADO DE CICLOS PARA EL ACCESO DE LA MEMORIA DE VIDEO POR LA CPU DURANTE UN MODO DE ALTA VELOCIDAD, PERO ADEMAS EL ARBITRAJE PERMITE A LA CPU ACCEDER DURANTE LOS PERIODOS DE NO USO DE LA PANTALLA DE TAL FORMA QUE LA CPU PUEDA ADQUIRIR MAS CICLOS SI LOS NECESITASE. EN UN MODO DE BAJA VELOCIDAD, EL ARBITRAJE SE PRODUCE TANTO EN LOS PERIODOS DE REPRESENTACION COMO EN LOS PERIODOS DE NO REPRESENTACION DE TAL FORMA QUE LA CPU PUEDA ADQUIRIR CICLO DE MEMORIA SOBRE SUS NECESIDADES BASICAS.
ES198787115759T 1987-03-20 1987-10-27 Sistema de ordenador con subsistema de video. Expired - Lifetime ES2036559T3 (es)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US2880187A 1987-03-20 1987-03-20

Publications (1)

Publication Number Publication Date
ES2036559T3 true ES2036559T3 (es) 1993-06-01

Family

ID=21845511

Family Applications (1)

Application Number Title Priority Date Filing Date
ES198787115759T Expired - Lifetime ES2036559T3 (es) 1987-03-20 1987-10-27 Sistema de ordenador con subsistema de video.

Country Status (20)

Country Link
EP (1) EP0283565B1 (es)
JP (1) JPH0766319B2 (es)
KR (1) KR950005230B1 (es)
CN (1) CN1021152C (es)
AR (1) AR241460A1 (es)
AT (1) ATE84162T1 (es)
BE (1) BE1001181A3 (es)
BR (1) BR8801254A (es)
CA (1) CA1297601C (es)
DE (3) DE3783358T2 (es)
ES (1) ES2036559T3 (es)
FR (1) FR2612662B1 (es)
GB (1) GB2202719B (es)
HK (1) HK33592A (es)
IT (1) IT1216769B (es)
MY (1) MY102808A (es)
NL (1) NL186120C (es)
PH (1) PH27199A (es)
SG (1) SG5092G (es)
SU (1) SU1523058A3 (es)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB8908612D0 (en) * 1989-04-17 1989-06-01 Quantel Ltd Video graphics system
GB2247139B (en) * 1990-08-09 1994-07-20 Research Machines Ltd Scheduling drawing operations of moving images

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4117469A (en) * 1976-12-20 1978-09-26 Levine Michael R Computer assisted display processor having memory sharing by the computer and the processor
GB2084836B (en) * 1980-10-06 1984-05-23 Standard Microsyst Smc Video processor and controller
JPS588348A (ja) * 1981-07-07 1983-01-18 Sony Corp 出力表示用メモリの制御回路
US4408200A (en) * 1981-08-12 1983-10-04 International Business Machines Corporation Apparatus and method for reading and writing text characters in a graphics display
JPS5960478A (ja) * 1982-09-30 1984-04-06 キヤノン株式会社 ビデオ用記憶装置書き換え方式
JPS59116846A (ja) * 1982-12-23 1984-07-05 Matsushita Electric Ind Co Ltd 中央演算装置の制御装置
US4577344A (en) * 1983-01-17 1986-03-18 Automatix Incorporated Vision system
US4511965A (en) * 1983-03-21 1985-04-16 Zenith Electronics Corporation Video ram accessing system
JPS6032089A (ja) * 1983-08-03 1985-02-19 松下電器産業株式会社 Ｃｒｔ表示端末装置
US4580135A (en) * 1983-08-12 1986-04-01 International Business Machines Corporation Raster scan display system
JPS60220386A (ja) * 1984-04-17 1985-11-05 三菱電機株式会社 フレ−ムメモリアクセス方式
EP0182454B1 (en) * 1984-07-23 1994-02-02 Texas Instruments Incorporated Video system controller with a row address override circuit
GB8608776D0 (en) * 1986-04-10 1986-05-14 Sinclair Res Ltd Video memory contention mechanism

Also Published As

Publication number Publication date
JPH0766319B2 (ja) 1995-07-19
JPS63231616A (ja) 1988-09-27
DE8803581U1 (de) 1988-11-24
GB8725114D0 (en) 1987-12-02
KR880011645A (ko) 1988-10-29
CN88100948A (zh) 1988-09-28
IT1216769B (it) 1990-03-08
SG5092G (en) 1992-03-20
NL186120B (nl) 1990-04-17
BR8801254A (pt) 1988-10-25
EP0283565A3 (en) 1989-06-21
FR2612662A1 (fr) 1988-09-23
CA1297601C (en) 1992-03-17
DE3783358D1 (de) 1993-02-11
NL8800626A (nl) 1988-10-17
DE3808832A1 (de) 1988-09-29
DE3808832C2 (es) 1992-03-12
DE3783358T2 (de) 1993-07-01
AR241460A1 (es) 1992-07-31
FR2612662B1 (fr) 1990-06-01
ATE84162T1 (de) 1993-01-15
CN1021152C (zh) 1993-06-09
BE1001181A3 (fr) 1989-08-08
MY102808A (en) 1992-11-30
PH27199A (en) 1993-04-16
KR950005230B1 (ko) 1995-05-22
NL186120C (nl) 1990-09-17
SU1523058A3 (ru) 1989-11-15
GB2202719A (en) 1988-09-28
EP0283565A2 (en) 1988-09-28
HK33592A (en) 1992-05-15
GB2202719B (en) 1991-07-24
EP0283565B1 (en) 1992-12-30
IT8819554A0 (it) 1988-02-26

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