ES2070822T3 - Microprocesador con memoria cache selectiva. - Google Patents
Microprocesador con memoria cache selectiva.Info
- Publication number
- ES2070822T3 ES2070822T3 ES87307646T ES87307646T ES2070822T3 ES 2070822 T3 ES2070822 T3 ES 2070822T3 ES 87307646 T ES87307646 T ES 87307646T ES 87307646 T ES87307646 T ES 87307646T ES 2070822 T3 ES2070822 T3 ES 2070822T3
- Authority
- ES
- Spain
- Prior art keywords
- cache memory
- memory
- selective cache
- instructions
- program
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- PWPJGUXAGUPAHP-UHFFFAOYSA-N lufenuron Chemical compound C1=C(Cl)C(OC(F)(F)C(C(F)(F)F)F)=CC(Cl)=C1NC(=O)NC(=O)C1=C(F)C=CC=C1F PWPJGUXAGUPAHP-UHFFFAOYSA-N 0.000 abstract 3
- 238000013500 data storage Methods 0.000 abstract 1
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0844—Multiple simultaneous or quasi-simultaneous cache accessing
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Software Systems (AREA)
- Memory System Of A Hierarchy Structure (AREA)
- Advance Control (AREA)
- Complex Calculations (AREA)
Abstract
SE DESCRIBE UN SISTEMA DE PROCESAMIENTO DE SEÑALES (10), EL CUAL TIENE UN PROCESADOR (12), UNA MEMORIA DE ACCESO ALEATORIO (14) PARA ALMACENAMIENTO DE DATOS, UNA MEMORIA DE SOLO LECTURA (16) PARA ALMACENAMIENTO DE COEFICIENTES E INSTRUCCIONES, Y UNA MEMORIA CACHE SELECTIVA (18) PARA ALMACENAMIENTO DE INSTRUCCIONES QUE REQUIEREN ALTA CAPACIDAD, Y SUS BUSES ASOCIADOS. LAS INSTRUCCIONES SELECCIONADAS POR EL PROGRAMA SON ALMACENADAS EN LA MEMORIA CACHE SELECTIVA DURANTE SU PRIMERA LLAMADA DESDE LA MEMORIA DE SOLO LECTURA, PARA POSTERIOR USO EN EL PROGRAMA. SE PUEDE USAR UN SECUENCIADOR DE DIRECCION COMO UNIDAD DE CONTROL, PARA EJECUTAR LOS DATOS ALMACENADOS EN LA MEMORIA CACHE SELECTIVA. ESTE, GENERA UNA SECUENCIA DE DIRECCIONES REPETITIVAMENTE, CUENTA EL NUMERO DE ITERACIONES DE LA SECUENCIA DE DIRECCIONES, E INFORMA AL CONTROLADOR CUANDO UN CIERTO NUMERO DE ITERACIONES HAN SIDO COMPLETADAS. ESTO CREA UNA INSTRUCCION CONDICIONAL DERIVADA EN EL PROGRAMA DEL SISTEMA DE PROCESAMIENTO DE SEÑALES (10).
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US06/904,544 US4896264A (en) | 1986-09-08 | 1986-09-08 | Microprocess with selective cache memory |
Publications (1)
Publication Number | Publication Date |
---|---|
ES2070822T3 true ES2070822T3 (es) | 1995-06-16 |
Family
ID=25419337
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
ES87307646T Expired - Lifetime ES2070822T3 (es) | 1986-09-08 | 1987-08-28 | Microprocesador con memoria cache selectiva. |
Country Status (7)
Country | Link |
---|---|
US (1) | US4896264A (es) |
EP (1) | EP0260837B1 (es) |
JP (1) | JP2567411B2 (es) |
KR (1) | KR940006916B1 (es) |
CA (1) | CA1289265C (es) |
DE (1) | DE3751252T2 (es) |
ES (1) | ES2070822T3 (es) |
Families Citing this family (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5179689A (en) * | 1987-03-13 | 1993-01-12 | Texas Instruments Incorporated | Dataprocessing device with instruction cache |
EP0389175A3 (en) * | 1989-03-15 | 1992-11-19 | Fujitsu Limited | Data prefetch system |
US5133058A (en) * | 1989-09-18 | 1992-07-21 | Sun Microsystems, Inc. | Page-tagging translation look-aside buffer for a computer memory system |
US5285527A (en) * | 1991-12-11 | 1994-02-08 | Northern Telecom Limited | Predictive historical cache memory |
GB2273179A (en) * | 1992-12-02 | 1994-06-08 | Ibm | Cache indexing in interative processes. |
US5432804A (en) * | 1993-11-16 | 1995-07-11 | At&T Corp. | Digital processor and viterbi decoder having shared memory |
US5832257A (en) * | 1995-12-29 | 1998-11-03 | Atmel Corporation | Digital signal processing method and system employing separate program and data memories to store data |
KR100395756B1 (ko) * | 2001-06-16 | 2003-08-21 | 삼성전자주식회사 | 캐쉬 메모리 및 이를 이용하는 마이크로 프로세서 |
AUPR881001A0 (en) * | 2001-11-12 | 2001-12-06 | Lake Technology Limited | Low latency computation in real time utilizing a dsp processor |
Family Cites Families (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5263038A (en) * | 1975-10-01 | 1977-05-25 | Hitachi Ltd | Data processing device |
US4141067A (en) * | 1977-06-13 | 1979-02-20 | General Automation | Multiprocessor system with cache memory |
US4181935A (en) * | 1977-09-02 | 1980-01-01 | Burroughs Corporation | Data processor with improved microprogramming |
AU518426B2 (en) * | 1977-11-22 | 1981-10-01 | Honeywell Information Systems Incorp. | Data processing system cache pre-read capability |
US4195342A (en) * | 1977-12-22 | 1980-03-25 | Honeywell Information Systems Inc. | Multi-configurable cache store system |
JPS54148335A (en) * | 1978-04-20 | 1979-11-20 | Nec Corp | Buffer control system |
US4197580A (en) * | 1978-06-08 | 1980-04-08 | Bell Telephone Laboratories, Incorporated | Data processing system including a cache memory |
US4306287A (en) * | 1979-08-31 | 1981-12-15 | Bell Telephone Laboratories, Incorporated | Special address generation arrangement |
EP0062978A3 (en) * | 1981-04-06 | 1982-12-22 | Secretary of State for Industry in Her Britannic Majesty's Gov. of the United Kingdom of Great Britain and Northern Ireland | Apparatus for assisting fault-finding in data processing systems |
DE3138972A1 (de) * | 1981-09-30 | 1983-04-14 | Siemens AG, 1000 Berlin und 8000 München | Onchip mikroprozessorchachespeichersystem und verfahren zu seinem betrieb |
US4521851A (en) * | 1982-10-13 | 1985-06-04 | Honeywell Information Systems Inc. | Central processor |
JPS61220004A (ja) * | 1985-03-26 | 1986-09-30 | Fanuc Ltd | 数値制御装置の画面表示方式 |
-
1986
- 1986-09-08 US US06/904,544 patent/US4896264A/en not_active Expired - Lifetime
-
1987
- 1987-08-27 CA CA000545551A patent/CA1289265C/en not_active Expired - Fee Related
- 1987-08-28 DE DE3751252T patent/DE3751252T2/de not_active Expired - Lifetime
- 1987-08-28 ES ES87307646T patent/ES2070822T3/es not_active Expired - Lifetime
- 1987-08-28 EP EP87307646A patent/EP0260837B1/en not_active Expired - Lifetime
- 1987-09-07 KR KR1019870009855A patent/KR940006916B1/ko not_active IP Right Cessation
- 1987-09-08 JP JP62223208A patent/JP2567411B2/ja not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
EP0260837A3 (en) | 1990-04-11 |
JPS6368931A (ja) | 1988-03-28 |
KR940006916B1 (ko) | 1994-07-29 |
EP0260837B1 (en) | 1995-04-19 |
DE3751252D1 (de) | 1995-05-24 |
EP0260837A2 (en) | 1988-03-23 |
DE3751252T2 (de) | 1995-08-24 |
CA1289265C (en) | 1991-09-17 |
US4896264A (en) | 1990-01-23 |
KR880004371A (ko) | 1988-06-07 |
JP2567411B2 (ja) | 1996-12-25 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
FG2A | Definitive protection |
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