JPS5781649A - Instruction word decoding system of information processor - Google Patents

Abstract

PURPOSE:To eliminate the use of a control instruction register of the latter half instruction word haivng a large quantity of hardware, by providing another operational code holding register having a small quantity of hardware, in order to decode the latter half instruction word. CONSTITUTION:An instruction word is held temporarily in a holding register 11. The first half 4 bytes of an operational code part (OP) are stored in the holding register 11, become an address input of a first half instruction decoder 12, and control information (a) of the first half instruction word is read out. At the same time, the OP code part of the instruction word holding register 11 is sotred in an operational code holding register 13. Subsequently, 4 bytes following the latter half instruction are stored in the holding register 11, the OP code stored in the register 13 becomes an address input of a latter half instruction word decoder 14, and control information (b) of the latter half word is read out. In this way, information required for generating the second oprand is obtained.