DE3572565D1 - Self-aligning method of forming an interconnection line over a contact hole in an integrated circuit - Google Patents

Self-aligning method of forming an interconnection line over a contact hole in an integrated circuit

Info

Publication number
DE3572565D1
DE3572565D1 DE8585401136T DE3572565T DE3572565D1 DE 3572565 D1 DE3572565 D1 DE 3572565D1 DE 8585401136 T DE8585401136 T DE 8585401136T DE 3572565 T DE3572565 T DE 3572565T DE 3572565 D1 DE3572565 D1 DE 3572565D1
Authority
DE
Germany
Prior art keywords
self
forming
integrated circuit
contact hole
interconnection line
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
DE8585401136T
Other languages
English (en)
Inventor
Joel Hartmann
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Commissariat a lEnergie Atomique et aux Energies Alternatives CEA
Original Assignee
Commissariat a lEnergie Atomique CEA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Commissariat a lEnergie Atomique CEA filed Critical Commissariat a lEnergie Atomique CEA
Application granted granted Critical
Publication of DE3572565D1 publication Critical patent/DE3572565D1/de
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/7684—Smoothing; Planarisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Electrodes Of Semiconductors (AREA)
DE8585401136T 1984-06-14 1985-06-10 Self-aligning method of forming an interconnection line over a contact hole in an integrated circuit Expired DE3572565D1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR8409313A FR2566181B1 (fr) 1984-06-14 1984-06-14 Procede d'autopositionnement d'une ligne d'interconnexion sur un trou de contact electrique d'un circuit integre

Publications (1)

Publication Number Publication Date
DE3572565D1 true DE3572565D1 (en) 1989-09-28

Family

ID=9305010

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8585401136T Expired DE3572565D1 (en) 1984-06-14 1985-06-10 Self-aligning method of forming an interconnection line over a contact hole in an integrated circuit

Country Status (5)

Country Link
US (1) US4624864A (de)
EP (1) EP0170544B1 (de)
JP (1) JPH0754809B2 (de)
DE (1) DE3572565D1 (de)
FR (1) FR2566181B1 (de)

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JPS5926808A (ja) * 1982-08-04 1984-02-13 Sanei Seisakusho:Kk 自動供給装置
US4975756A (en) * 1985-05-01 1990-12-04 Texas Instruments Incorporated SRAM with local interconnect
JP2581666B2 (ja) * 1985-09-06 1997-02-12 株式会社日立製作所 配線構造体の製造方法
KR900003618B1 (ko) * 1986-05-30 1990-05-26 후지쓰가부시끼가이샤 반도체장치 및 그 제조방법
JPS6334954A (ja) * 1986-07-29 1988-02-15 Nec Corp 半導体装置およびその製造方法
US5063175A (en) * 1986-09-30 1991-11-05 North American Philips Corp., Signetics Division Method for manufacturing a planar electrical interconnection utilizing isotropic deposition of conductive material
KR910006975B1 (ko) * 1986-12-19 1991-09-14 휴우즈 에어크라프트 캄파니 도전성 플러그로 집적 회로 상의 접점 및 비아를 충전하는 방법
US4837051A (en) * 1986-12-19 1989-06-06 Hughes Aircraft Company Conductive plug for contacts and vias on integrated circuits
GB2199183B (en) * 1986-12-23 1990-07-04 Gen Electric Plc Interconnection formation in multilayer circuits
US4884123A (en) * 1987-02-19 1989-11-28 Advanced Micro Devices, Inc. Contact plug and interconnect employing a barrier lining and a backfilled conductor material
US4960732A (en) * 1987-02-19 1990-10-02 Advanced Micro Devices, Inc. Contact plug and interconnect employing a barrier lining and a backfilled conductor material
CA1306072C (en) * 1987-03-30 1992-08-04 John E. Cronin Refractory metal - titanium nitride conductive structures and processes for forming the same
JPS63299251A (ja) * 1987-05-29 1988-12-06 Toshiba Corp 半導体装置の製造方法
JPH01108746A (ja) * 1987-10-21 1989-04-26 Toshiba Corp 半導体装置の製造方法
GB2212979A (en) * 1987-12-02 1989-08-02 Philips Nv Fabricating electrical connections,particularly in integrated circuit manufacture
JPH01147843A (ja) * 1987-12-03 1989-06-09 Mitsubishi Electric Corp 半導体装置の製造方法
US5055423A (en) * 1987-12-28 1991-10-08 Texas Instruments Incorporated Planarized selective tungsten metallization system
US4994410A (en) * 1988-04-04 1991-02-19 Motorola, Inc. Method for device metallization by forming a contact plug and interconnect using a silicide/nitride process
US4926237A (en) * 1988-04-04 1990-05-15 Motorola, Inc. Device metallization, device and method
FR2630588A1 (fr) * 1988-04-22 1989-10-27 Philips Nv Procede pour realiser une configuration d'interconnexion sur un dispositif semiconducteur notamment un circuit a densite d'integration elevee
US4822753A (en) * 1988-05-09 1989-04-18 Motorola, Inc. Method for making a w/tin contact
EP0346543A1 (de) * 1988-06-15 1989-12-20 BRITISH TELECOMMUNICATIONS public limited company Bipolarer Transistor
US4898841A (en) * 1988-06-16 1990-02-06 Northern Telecom Limited Method of filling contact holes for semiconductor devices and contact structures made by that method
FR2634317A1 (fr) * 1988-07-12 1990-01-19 Philips Nv Procede pour fabriquer un dispositif semiconducteur ayant au moins un niveau de prise de contact a travers des ouvertures de contact de petites dimensions
US5149672A (en) * 1988-08-01 1992-09-22 Nadia Lifshitz Process for fabricating integrated circuits having shallow junctions
US5104826A (en) * 1989-02-02 1992-04-14 Matsushita Electric Industrial Co., Ltd. Method for fabricating semiconductor integrated circuit device using an electrode wiring structure
US4961822A (en) * 1989-04-17 1990-10-09 Liao Kuan Y Fully recessed interconnection scheme with titanium-tungsten and selective CVD tungsten
JPH03156930A (ja) * 1989-11-15 1991-07-04 Sanyo Electric Co Ltd 半導体装置
US5141897A (en) * 1990-03-23 1992-08-25 At&T Bell Laboratories Method of making integrated circuit interconnection
US5242858A (en) * 1990-09-07 1993-09-07 Canon Kabushiki Kaisha Process for preparing semiconductor device by use of a flattening agent and diffusion
JP3068223B2 (ja) * 1991-02-12 2000-07-24 三菱電機株式会社 半導体装置の製造方
JPH04307933A (ja) * 1991-04-05 1992-10-30 Sony Corp タングステンプラグの形成方法
US5300813A (en) * 1992-02-26 1994-04-05 International Business Machines Corporation Refractory metal capped low resistivity metal conductor lines and vias
US5363550A (en) * 1992-12-23 1994-11-15 International Business Machines Corporation Method of Fabricating a micro-coaxial wiring structure
US5514622A (en) * 1994-08-29 1996-05-07 Cypress Semiconductor Corporation Method for the formation of interconnects and landing pads having a thin, conductive film underlying the plug or an associated contact of via hole
KR0137579B1 (ko) * 1994-11-30 1998-06-01 김주용 반도체 소자의 플러그 형성방법
KR100193100B1 (ko) * 1995-02-02 1999-06-15 모리시다 요이치 반도체장치 및 그 제조방법
US5624870A (en) * 1995-03-16 1997-04-29 United Microelectronics Corporation Method of contact planarization
US7294578B1 (en) * 1995-06-02 2007-11-13 Micron Technology, Inc. Use of a plasma source to form a layer during the formation of a semiconductor device
US5700716A (en) 1996-02-23 1997-12-23 Micron Technology, Inc. Method for forming low contact resistance contacts, vias, and plugs with diffusion barriers
US6004874A (en) * 1996-06-26 1999-12-21 Cypress Semiconductor Corporation Method for forming an interconnect
JPH1140664A (ja) * 1997-07-17 1999-02-12 Mitsubishi Electric Corp 半導体装置の製造方法
US5994211A (en) * 1997-11-21 1999-11-30 Lsi Logic Corporation Method and composition for reducing gate oxide damage during RF sputter clean
US6670717B2 (en) * 2001-10-15 2003-12-30 International Business Machines Corporation Structure and method for charge sensitive electrical devices
KR20040039778A (ko) * 2002-11-04 2004-05-12 주식회사 하이닉스반도체 반도체소자의 금속배선 형성방법
JP5343982B2 (ja) * 2009-02-16 2013-11-13 トヨタ自動車株式会社 半導体装置

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2547792C3 (de) * 1974-10-25 1978-08-31 Hitachi, Ltd., Tokio Verfahren zur Herstellung eines Halbleiterbauelementes
JPS5494196A (en) * 1977-12-30 1979-07-25 Ibm Metallic layer removing method
JPS5793548A (en) * 1980-12-03 1982-06-10 Fujitsu Ltd Manufacture of semiconductor device
US4361599A (en) * 1981-03-23 1982-11-30 National Semiconductor Corporation Method of forming plasma etched semiconductor contacts
JPS5810836A (ja) * 1981-07-13 1983-01-21 Oki Electric Ind Co Ltd 半導体装置
JPS5815250A (ja) * 1981-07-21 1983-01-28 Fujitsu Ltd 半導体装置の製造方法
US4544576A (en) * 1981-07-27 1985-10-01 International Business Machines Corporation Deep dielectric isolation by fused glass
US4392298A (en) * 1981-07-27 1983-07-12 Bell Telephone Laboratories, Incorporated Integrated circuit device connection process
JPS5982746A (ja) * 1982-11-04 1984-05-12 Toshiba Corp 半導体装置の電極配線方法
FR2537779B1 (fr) * 1982-12-10 1986-03-14 Commissariat Energie Atomique Procede de positionnement d'un trou de contact electrique entre deux lignes d'interconnexion d'un circuit integre
JPS59154040A (ja) * 1983-02-22 1984-09-03 Toshiba Corp 半導体装置の製造方法
DE3314879A1 (de) * 1983-04-25 1984-10-25 Siemens AG, 1000 Berlin und 8000 München Verfahren zum herstellen von stabilen, niederohmigen kontakten in integrierten halbleiterschaltungen

Also Published As

Publication number Publication date
JPH0754809B2 (ja) 1995-06-07
EP0170544A1 (de) 1986-02-05
EP0170544B1 (de) 1989-08-23
JPS6110256A (ja) 1986-01-17
FR2566181A1 (fr) 1985-12-20
FR2566181B1 (fr) 1986-08-22
US4624864A (en) 1986-11-25

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition