DE3434727C2 - - Google Patents

Info

Publication number
DE3434727C2
DE3434727C2 DE3434727A DE3434727A DE3434727C2 DE 3434727 C2 DE3434727 C2 DE 3434727C2 DE 3434727 A DE3434727 A DE 3434727A DE 3434727 A DE3434727 A DE 3434727A DE 3434727 C2 DE3434727 C2 DE 3434727C2
Authority
DE
Germany
Prior art keywords
thin film
silicon carbide
sic
oxide layer
silicon
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
DE3434727A
Other languages
German (de)
English (en)
Other versions
DE3434727A1 (de
Inventor
Akira Nara Jp Suzuki
Katsuki Sakai Osaka Jp Furukawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sharp Corp
Original Assignee
Sharp Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sharp Corp filed Critical Sharp Corp
Publication of DE3434727A1 publication Critical patent/DE3434727A1/de
Application granted granted Critical
Publication of DE3434727C2 publication Critical patent/DE3434727C2/de
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/83—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge
    • H10D62/832—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge being Group IV materials comprising two or more elements, e.g. SiGe
    • H10D62/8325—Silicon carbide
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D64/01366—

Landscapes

  • Electrodes Of Semiconductors (AREA)
  • Formation Of Insulating Films (AREA)
DE19843434727 1983-09-24 1984-09-21 Verfahren zur herstellung von siliciumcarbid(sic)-metalloxidhalbleiter-(mos)-bauteilen Granted DE3434727A1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58177482A JPS6066866A (ja) 1983-09-24 1983-09-24 炭化珪素ｍｏｓ構造の製造方法

Publications (2)

Publication Number Publication Date
DE3434727A1 DE3434727A1 (de) 1985-04-11
DE3434727C2 true DE3434727C2 (OSRAM) 1987-12-17

Family

ID=16031676

Family Applications (1)

Application Number Title Priority Date Filing Date
DE19843434727 Granted DE3434727A1 (de) 1983-09-24 1984-09-21 Verfahren zur herstellung von siliciumcarbid(sic)-metalloxidhalbleiter-(mos)-bauteilen

Country Status (2)

Country Link
JP (1) JPS6066866A (OSRAM)
DE (1) DE3434727A1 (OSRAM)

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2615390B2 (ja) * 1985-10-07 1997-05-28 工業技術院長 炭化シリコン電界効果トランジスタの製造方法
JPH0728024B2 (ja) * 1986-03-10 1995-03-29 工業技術院長 炭化けい素を用いた半導体素子
US5612260A (en) * 1992-06-05 1997-03-18 Cree Research, Inc. Method of obtaining high quality silicon dioxide passivation on silicon carbide and resulting passivated structures
US5459107A (en) * 1992-06-05 1995-10-17 Cree Research, Inc. Method of obtaining high quality silicon dioxide passivation on silicon carbide and resulting passivated structures
KR20000068738A (ko) * 1997-08-13 2000-11-25 모리시타 요이찌 반도체기판 및 반도체소자
FR2801723B1 (fr) * 1999-11-25 2003-09-05 Commissariat Energie Atomique Couche de silicium tres sensible a l'oxygene et procede d'obtention de cette couche
JP2006216918A (ja) * 2005-02-07 2006-08-17 Kyoto Univ 半導体素子の製造方法
US8841682B2 (en) * 2009-08-27 2014-09-23 Cree, Inc. Transistors with a gate insulation layer having a channel depleting interfacial charge and related fabrication methods
JP5605005B2 (ja) * 2010-06-16 2014-10-15 住友電気工業株式会社 炭化珪素半導体装置の製造方法および炭化珪素半導体装置の製造装置
JP2012004275A (ja) * 2010-06-16 2012-01-05 Sumitomo Electric Ind Ltd 炭化珪素半導体装置の製造方法
JP2012004269A (ja) * 2010-06-16 2012-01-05 Sumitomo Electric Ind Ltd 炭化珪素半導体装置の製造方法および炭化珪素半導体装置の製造装置
GB2483702A (en) * 2010-09-17 2012-03-21 Ge Aviat Systems Ltd Method for the manufacture of a Silicon Carbide, Silicon Oxide interface having reduced interfacial carbon gettering
JP2025017198A (ja) * 2023-07-24 2025-02-05 株式会社東芝 半導体装置の製造方法

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
IT1089298B (it) * 1977-01-17 1985-06-18 Mostek Corp Procedimento per fabbricare un dispositivo semiconduttore

Also Published As

Publication number Publication date
DE3434727A1 (de) 1985-04-11
JPS6066866A (ja) 1985-04-17
JPH055182B2 (OSRAM) 1993-01-21

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Legal Events

Date Code Title Description
OP8 Request for examination as to paragraph 44 patent law
D2 Grant after examination
8364 No opposition during term of opposition
8328 Change in the person/name/address of the agent

Free format text: PATENTANWAELTE MUELLER & HOFFMANN, 81667 MUENCHEN

8339 Ceased/non-payment of the annual fee