DE3889762T2 - Elektrische Schaltung mit supraleitender Mehrschichtstruktur und Herstellungsverfahren dafür. - Google Patents

Elektrische Schaltung mit supraleitender Mehrschichtstruktur und Herstellungsverfahren dafür.

Info

Publication number
DE3889762T2
DE3889762T2 DE3889762T DE3889762T DE3889762T2 DE 3889762 T2 DE3889762 T2 DE 3889762T2 DE 3889762 T DE3889762 T DE 3889762T DE 3889762 T DE3889762 T DE 3889762T DE 3889762 T2 DE3889762 T2 DE 3889762T2
Authority
DE
Germany
Prior art keywords
manufacturing process
electrical circuit
multilayer structure
process therefor
superconducting multilayer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE3889762T
Other languages
English (en)
Other versions
DE3889762D1 (de
Inventor
Shunpei Yamazaki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Semiconductor Energy Laboratory Co Ltd
Original Assignee
Semiconductor Energy Laboratory Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from JP62081487A external-priority patent/JPH0634412B2/ja
Priority claimed from JP63022384A external-priority patent/JPH01197308A/ja
Application filed by Semiconductor Energy Laboratory Co Ltd filed Critical Semiconductor Energy Laboratory Co Ltd
Application granted granted Critical
Publication of DE3889762D1 publication Critical patent/DE3889762D1/de
Publication of DE3889762T2 publication Critical patent/DE3889762T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N60/00—Superconducting devices
    • H10N60/10—Junction-based devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53285—Conductive materials containing superconducting materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76886—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances
    • H01L21/76891—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances by using superconducting materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49866—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers characterised by the materials
    • H01L23/49888—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers characterised by the materials the conductive materials containing superconducting material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/437—Superconductor materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N60/00—Superconducting devices
    • H10N60/01—Manufacture or treatment
    • H10N60/0268—Manufacture or treatment of devices comprising copper oxide
    • H10N60/0296—Processes for depositing or forming superconductor layers
    • H10N60/0576—Processes for depositing or forming superconductor layers characterised by the substrate
    • H10N60/0632—Intermediate layers, e.g. for growth control
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N60/00—Superconducting devices
    • H10N60/01—Manufacture or treatment
    • H10N60/0268—Manufacture or treatment of devices comprising copper oxide
    • H10N60/0661—After-treatment, e.g. patterning
    • H10N60/0688—Etching
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N60/00—Superconducting devices
    • H10N60/01—Manufacture or treatment
    • H10N60/0268—Manufacture or treatment of devices comprising copper oxide
    • H10N60/0661—After-treatment, e.g. patterning
    • H10N60/0716—Passivation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/095—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
    • H01L2924/097—Glass-ceramics, e.g. devitrified glass
    • H01L2924/09701—Low temperature co-fired ceramic [LTCC]
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S428/00—Stock material or miscellaneous articles
    • Y10S428/922—Static electricity metal bleed-off metallic stock
    • Y10S428/9265—Special properties
    • Y10S428/93—Electric superconducting
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S505/00—Superconductor technology: apparatus, material, process
    • Y10S505/70—High TC, above 30 k, superconducting device, article, or structured stock
    • Y10S505/701—Coated or thin film device, i.e. active or passive
    • Y10S505/703—Microelectronic device with superconducting conduction line
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T428/00—Stock material or miscellaneous articles
    • Y10T428/24—Structurally defined web or sheet [e.g., overall dimension, etc.]
    • Y10T428/24802—Discontinuous or differential coating, impregnation or bond [e.g., artwork, printing, retouched photograph, etc.]
DE3889762T 1987-04-01 1988-03-31 Elektrische Schaltung mit supraleitender Mehrschichtstruktur und Herstellungsverfahren dafür. Expired - Fee Related DE3889762T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP62081487A JPH0634412B2 (ja) 1987-04-01 1987-04-01 超電導体装置
JP63022384A JPH01197308A (ja) 1988-02-01 1988-02-01 炭素膜で保護された酸化物超伝導体およびその作製方法

Publications (2)

Publication Number Publication Date
DE3889762D1 DE3889762D1 (de) 1994-07-07
DE3889762T2 true DE3889762T2 (de) 1994-09-08

Family

ID=26359589

Family Applications (1)

Application Number Title Priority Date Filing Date
DE3889762T Expired - Fee Related DE3889762T2 (de) 1987-04-01 1988-03-31 Elektrische Schaltung mit supraleitender Mehrschichtstruktur und Herstellungsverfahren dafür.

Country Status (5)

Country Link
US (1) US4960751A (de)
EP (1) EP0285445B1 (de)
KR (1) KR960006207B1 (de)
CN (1) CN1033543C (de)
DE (1) DE3889762T2 (de)

Families Citing this family (32)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0282012A3 (de) * 1987-03-09 1989-09-13 Semiconductor Energy Laboratory Co., Ltd. Supraleitende Halbleiteranordnung
US5274268A (en) * 1987-04-01 1993-12-28 Semiconductor Energy Laboratory Co., Ltd. Electric circuit having superconducting layered structure
US5248658A (en) * 1987-04-07 1993-09-28 Semiconductor Energy Laboratory Co., Ltd. Method of manufacturing a superconducting oxide pattern by laser sublimation
US5401716A (en) * 1987-04-15 1995-03-28 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing superconducting patterns
AU599223B2 (en) * 1987-04-15 1990-07-12 Semiconductor Energy Laboratory Co. Ltd. Superconducting ceramic pattern and its manufacturing method
CA1329952C (en) 1987-04-27 1994-05-31 Yoshihiko Imanaka Multi-layer superconducting circuit substrate and process for manufacturing same
US5232903A (en) * 1987-05-06 1993-08-03 Semiconductor Energy Laboratory Co., Ltd. Oxide superconducting device having uniform oxygen concentration
CA1326976C (en) * 1987-05-26 1994-02-15 Satoshi Takano Superconducting member
NL8701718A (nl) * 1987-07-21 1989-02-16 Philips Nv Werkwijze voor het aanbrengen van dunne lagen van oxidisch supergeleidend materiaal.
DE3889263T2 (de) * 1987-08-24 1994-08-11 Semiconductor Energy Lab Elektronische Anordnungen unter Verwendung von supraleitenden Materialien.
US5225394A (en) * 1987-08-31 1993-07-06 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing high Tc superconducting circuits
GB2211662B (en) * 1988-01-16 1991-01-16 Int Computers Ltd Multichip carriers
US5171732A (en) * 1988-12-23 1992-12-15 Troy Investments, Inc. Method of making a josephson junction
US5084437A (en) * 1990-02-28 1992-01-28 Westinghouse Electric Corp. Method for making high-current, ohmic contacts between semiconductors and oxide superconductors
JPH05894A (ja) * 1990-06-28 1993-01-08 Sumitomo Electric Ind Ltd 複合酸化物超電導薄膜
US5212626A (en) * 1990-11-09 1993-05-18 International Business Machines Corporation Electronic packaging and cooling system using superconductors for power distribution
CA2062294C (en) * 1991-03-04 1997-01-14 Hiroshi Inada Thin film of oxide superconductor possessing locally different crystal orientations and processes for preparing the same
WO1992020092A1 (en) * 1991-05-08 1992-11-12 Superconductor Technologies, Inc. Passivation coating for superconducting thin film device
EP0570720A1 (de) * 1992-05-20 1993-11-24 Sumitomo Electric Industries, Ltd. Leitendes oder superleitendes stabilisiertes Kohlenstoff-Cluster-Material sowie Herstellung und Verwendung
US5455432A (en) * 1994-10-11 1995-10-03 Kobe Steel Usa Diamond semiconductor device with carbide interlayer
US5818071A (en) * 1995-02-02 1998-10-06 Dow Corning Corporation Silicon carbide metal diffusion barrier layer
JP4355039B2 (ja) * 1998-05-07 2009-10-28 東京エレクトロン株式会社 半導体装置及び半導体装置の製造方法
FI19992757A (fi) 1999-12-22 2001-06-23 Nanoway Oy Menetelmä tunneliliitoskomponentin stabiloimiseksi ja stabiloitu tunneliliitoskomponentti
US6518648B1 (en) * 2000-09-27 2003-02-11 Advanced Micro Devices, Inc. Superconductor barrier layer for integrated circuit interconnects
US20060060977A1 (en) * 2004-09-22 2006-03-23 Kabushiki Kaisha Toshiba Semiconductor device
WO2010006000A1 (en) * 2008-07-08 2010-01-14 Sandisk 3D, Llc Carbon-based resistivity-switching materials and methods of forming the same
US8470646B2 (en) * 2008-12-31 2013-06-25 Sandisk 3D Llc Modulation of resistivity in carbon-based read-writeable materials
US9653398B1 (en) * 2015-12-08 2017-05-16 Northrop Grumman Systems Corporation Non-oxide based dielectrics for superconductor devices
US10608159B2 (en) 2016-11-15 2020-03-31 Northrop Grumman Systems Corporation Method of making a superconductor device
US10276504B2 (en) 2017-05-17 2019-04-30 Northrop Grumman Systems Corporation Preclean and deposition methodology for superconductor interconnects
US10763419B2 (en) 2017-06-02 2020-09-01 Northrop Grumman Systems Corporation Deposition methodology for superconductor interconnects
US10985059B2 (en) 2018-11-01 2021-04-20 Northrop Grumman Systems Corporation Preclean and dielectric deposition methodology for superconductor interconnect fabrication

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US39A (en) * 1836-10-04 Purifying- wateil for use in steamt-boilees
US3352008A (en) * 1963-05-03 1967-11-14 Nat Res Corp Process of bonding copper foil to foil containing superconductive layer such as niobium stannide
US3432783A (en) * 1967-08-24 1969-03-11 Atomic Energy Commission Superconductor ribbon
US3912611A (en) * 1973-03-12 1975-10-14 Bell Telephone Labor Inc Film material and devices using same
FR2273385B1 (de) * 1974-05-29 1976-10-15 Comp Generale Electricite
JPS5887884A (ja) * 1981-11-20 1983-05-25 Nippon Telegr & Teleph Corp <Ntt> 酸化物超伝導体回路の電極形成方法
JPH0635323B2 (ja) * 1982-06-25 1994-05-11 株式会社日立製作所 表面処理方法
US4470190A (en) * 1982-11-29 1984-09-11 At&T Bell Laboratories Josephson device fabrication method
JPH0648733B2 (ja) * 1984-01-25 1994-06-22 株式会社日立製作所 極低温用半導体装置
JPH0682839B2 (ja) * 1984-08-21 1994-10-19 セイコー電子工業株式会社 表示用パネルの製造方法
JPH0710007B2 (ja) * 1985-03-04 1995-02-01 株式会社日立製作所 超電導トランジスタ集積回路
DE3810494C2 (de) * 1987-03-27 1998-08-20 Hitachi Ltd Integrierte Halbleiterschaltungseinrichtung mit supraleitender Schicht
CA1329952C (en) * 1987-04-27 1994-05-31 Yoshihiko Imanaka Multi-layer superconducting circuit substrate and process for manufacturing same
JPH064278A (ja) * 1992-06-17 1994-01-14 Yaskawa Electric Corp 小型計算機によるフロー図作成方法

Also Published As

Publication number Publication date
KR880013427A (ko) 1988-11-30
KR960006207B1 (ko) 1996-05-09
EP0285445A3 (en) 1989-09-06
CN88102047A (zh) 1988-10-19
EP0285445B1 (de) 1994-06-01
EP0285445A2 (de) 1988-10-05
DE3889762D1 (de) 1994-07-07
CN1033543C (zh) 1996-12-11
US4960751A (en) 1990-10-02

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Legal Events

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8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee