DE3412677C2 - - Google Patents

Info

Publication number
DE3412677C2
DE3412677C2 DE3412677A DE3412677A DE3412677C2 DE 3412677 C2 DE3412677 C2 DE 3412677C2 DE 3412677 A DE3412677 A DE 3412677A DE 3412677 A DE3412677 A DE 3412677A DE 3412677 C2 DE3412677 C2 DE 3412677C2
Authority
DE
Germany
Prior art keywords
circuit
memory
signal
line
information
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
DE3412677A
Other languages
German (de)
English (en)
Other versions
DE3412677A1 (de
Inventor
Yutaka Tokio/Tokyo Jp Kumagai
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Oki Electric Industry Co Ltd
Original Assignee
Oki Electric Industry Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Oki Electric Industry Co Ltd filed Critical Oki Electric Industry Co Ltd
Publication of DE3412677A1 publication Critical patent/DE3412677A1/de
Application granted granted Critical
Publication of DE3412677C2 publication Critical patent/DE3412677C2/de
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/14—Error detection or correction of the data by redundancy in operation
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/88—Masking faults in memories by using spares or by reconfiguring with partially good memories

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
DE19843412677 1983-04-04 1984-04-04 Halbleiterspeichervorrichtung mit selbstkorrekturschaltung Granted DE3412677A1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58058023A JPS59185098A (ja) 1983-04-04 1983-04-04 自己診断回路内蔵型半導体メモリ装置

Publications (2)

Publication Number Publication Date
DE3412677A1 DE3412677A1 (de) 1984-10-11
DE3412677C2 true DE3412677C2 (ja) 1988-08-25

Family

ID=13072352

Family Applications (1)

Application Number Title Priority Date Filing Date
DE19843412677 Granted DE3412677A1 (de) 1983-04-04 1984-04-04 Halbleiterspeichervorrichtung mit selbstkorrekturschaltung

Country Status (4)

Country Link
US (1) US4615030A (ja)
JP (1) JPS59185098A (ja)
DE (1) DE3412677A1 (ja)
GB (1) GB2137784B (ja)

Families Citing this family (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5177743A (en) * 1982-02-15 1993-01-05 Hitachi, Ltd. Semiconductor memory
US4943967A (en) * 1982-02-15 1990-07-24 Hitachi, Ltd. Semiconductor memory with an improved dummy cell arrangement and with a built-in error correction code circuit
JPH0731918B2 (ja) * 1985-03-20 1995-04-10 株式会社東芝 読出し専用メモリ
US4783782A (en) * 1985-12-12 1988-11-08 Alcatel U.S.A. Corporation Manufacturing test data storage apparatus for dynamically reconfigurable cellular array processor chip
US4733393A (en) * 1985-12-12 1988-03-22 Itt Corporation Test method and apparatus for cellular array processor chip
JPH0748090B2 (ja) * 1987-04-09 1995-05-24 オリンパス光学工業株式会社 手術用顕微鏡
JP2664236B2 (ja) * 1989-02-01 1997-10-15 富士通株式会社 半導体記憶装置
US5267204A (en) * 1991-10-18 1993-11-30 Texas Instruments Incorporated Method and circuitry for masking data in a memory device
US5450426A (en) * 1992-12-18 1995-09-12 Unisys Corporation Continuous error detection using duplicate core memory cells
DE69323076T2 (de) * 1993-07-26 1999-06-24 Stmicroelectronics S.R.L., Agrate Brianza, Mailand/Milano Verfahren zur Erkennung fehlerhafter Elemente eines redundanten Halbleiterspeichers
US5511164A (en) * 1995-03-01 1996-04-23 Unisys Corporation Method and apparatus for determining the source and nature of an error within a computer system
JP3207727B2 (ja) * 1995-10-03 2001-09-10 株式会社東芝 半導体集積回路およびその応用装置
US5968190A (en) * 1996-10-31 1999-10-19 Cypress Semiconductor Corp. Redundancy method and circuit for self-repairing memory arrays
JPH10229174A (ja) * 1997-02-18 1998-08-25 Mitsubishi Electric Corp 半導体記憶装置の製造方法
US5745403A (en) * 1997-02-28 1998-04-28 Ramtron International Corporation System and method for mitigating imprint effect in ferroelectric random access memories utilizing a complementary data path
US7069494B2 (en) * 2003-04-17 2006-06-27 International Business Machines Corporation Application of special ECC matrix for solving stuck bit faults in an ECC protected mechanism
US7471569B2 (en) * 2005-06-15 2008-12-30 Infineon Technologies Ag Memory having parity error correction
US8365044B2 (en) * 2007-04-23 2013-01-29 Agere Systems Inc. Memory device with error correction based on automatic logic inversion
US9411668B2 (en) * 2014-01-14 2016-08-09 Nvidia Corporation Approach to predictive verification of write integrity in a memory driver

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3096511A (en) * 1959-02-25 1963-07-02 Ibm Apparatus for effecting concurrent record, read and checking operations
DE2036517B2 (de) * 1970-07-23 1972-10-19 Ibm Deutschland Gmbh, 7000 Stuttgart Verfahren zum betrieb eines schadhafte speicherelemente enthaltenden speichers fuer programmgesteuerte elektronische datenverarbeitungsanlagen
US3768071A (en) * 1972-01-24 1973-10-23 Ibm Compensation for defective storage positions
FR2246023B1 (ja) * 1973-09-05 1976-10-01 Honeywell Bull Soc Ind
US4045779A (en) * 1976-03-15 1977-08-30 Xerox Corporation Self-correcting memory circuit
US4228528B2 (en) * 1979-02-09 1992-10-06 Memory with redundant rows and columns
JPS5613585A (en) * 1979-07-13 1981-02-09 Hitachi Ltd Semiconductor memory circuit
US4363125A (en) * 1979-12-26 1982-12-07 International Business Machines Corporation Memory readback check method and apparatus
US4365332A (en) * 1980-11-03 1982-12-21 Fairchild Camera And Instrument Corp. Method and circuitry for correcting errors in recirculating memories
JPS589298A (ja) * 1981-07-09 1983-01-19 Toshiba Corp 冗長度を有する半導体記憶装置
JPS583198A (ja) * 1981-06-30 1983-01-08 Toshiba Corp 半導体記憶装置
JPS595497A (ja) * 1982-07-02 1984-01-12 Hitachi Ltd 半導体ｒｏｍ

Also Published As

Publication number Publication date
GB2137784A (en) 1984-10-10
JPS59185098A (ja) 1984-10-20
GB2137784B (en) 1987-01-07
GB8408670D0 (en) 1984-05-16
JPS6236317B2 (ja) 1987-08-06
US4615030A (en) 1986-09-30
DE3412677A1 (de) 1984-10-11

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Legal Events

Date Code Title Description
OP8 Request for examination as to paragraph 44 patent law
8128 New person/name/address of the agent

Representative=s name: BETTEN, J., DIPL.-ING., PAT.-ANW., 8000 MUENCHEN

D2 Grant after examination
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee