DE68925090T2 - Speicherschaltung mit verbesserter Redundanzstruktur - Google Patents

Speicherschaltung mit verbesserter Redundanzstruktur

Info

Publication number
DE68925090T2
DE68925090T2 DE1989625090 DE68925090T DE68925090T2 DE 68925090 T2 DE68925090 T2 DE 68925090T2 DE 1989625090 DE1989625090 DE 1989625090 DE 68925090 T DE68925090 T DE 68925090T DE 68925090 T2 DE68925090 T2 DE 68925090T2
Authority
DE
Germany
Prior art keywords
memory circuit
memory
output circuits
redundancy structure
improved redundancy
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE1989625090
Other languages
English (en)
Other versions
DE68925090D1 (de
Inventor
Kugao Ohuchi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Electronics Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Publication of DE68925090D1 publication Critical patent/DE68925090D1/de
Application granted granted Critical
Publication of DE68925090T2 publication Critical patent/DE68925090T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
    • G11C29/84—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved access time or stability
    • G11C29/848—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved access time or stability by adjacent switching

Landscapes

  • For Increasing The Reliability Of Semiconductor Memories (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Semiconductor Memories (AREA)
  • Dram (AREA)
DE1989625090 1988-09-27 1989-09-26 Speicherschaltung mit verbesserter Redundanzstruktur Expired - Fee Related DE68925090T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63241906A JPH0289299A (ja) 1988-09-27 1988-09-27 半導体記憶装置

Publications (2)

Publication Number Publication Date
DE68925090D1 DE68925090D1 (de) 1996-01-25
DE68925090T2 true DE68925090T2 (de) 1996-07-04

Family

ID=17081312

Family Applications (1)

Application Number Title Priority Date Filing Date
DE1989625090 Expired - Fee Related DE68925090T2 (de) 1988-09-27 1989-09-26 Speicherschaltung mit verbesserter Redundanzstruktur

Country Status (3)

Country Link
EP (1) EP0361404B1 (de)
JP (1) JPH0289299A (de)
DE (1) DE68925090T2 (de)

Families Citing this family (25)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB8926004D0 (en) * 1989-11-17 1990-01-10 Inmos Ltd Repairable memory circuit
JPH0476996A (ja) * 1990-07-18 1992-03-11 Cmk Corp プリント配線板の製造方法
FR2666917B1 (fr) * 1990-09-14 1994-02-18 Samsung Electronics Co Ltd Dispositif de memorisation a double acces.
US5265054A (en) * 1990-12-14 1993-11-23 Sgs-Thomson Microelectronics, Inc. Semiconductor memory with precharged redundancy multiplexing
EP0490680B1 (de) * 1990-12-14 1996-10-02 STMicroelectronics, Inc. Halbleiterspeicher mit Multiplex-Redundanz
JP2909328B2 (ja) * 1992-11-02 1999-06-23 株式会社東芝 フィールドプログラマブルゲートアレイ
US5434514A (en) * 1992-11-19 1995-07-18 Altera Corporation Programmable logic devices with spare circuits for replacement of defects
US5764587A (en) * 1995-06-07 1998-06-09 International Business Machines Corporation Static wordline redundancy memory device
US5608678A (en) * 1995-07-31 1997-03-04 Sgs-Thomson Microelectronics, Inc. Column redundancy of a multiple block memory architecture
US5592102A (en) * 1995-10-19 1997-01-07 Altera Corporation Means and apparatus to minimize the effects of silicon processing defects in programmable logic devices
US5771195A (en) * 1995-12-29 1998-06-23 Sgs-Thomson Microelectronics, Inc. Circuit and method for replacing a defective memory cell with a redundant memory cell
US5841709A (en) * 1995-12-29 1998-11-24 Stmicroelectronics, Inc. Memory having and method for testing redundant memory cells
US5612918A (en) * 1995-12-29 1997-03-18 Sgs-Thomson Microelectronics, Inc. Redundancy architecture
US5790462A (en) * 1995-12-29 1998-08-04 Sgs-Thomson Microelectronics, Inc. Redundancy control
US6037799A (en) * 1995-12-29 2000-03-14 Stmicroelectronics, Inc. Circuit and method for selecting a signal
US6034536A (en) * 1997-02-05 2000-03-07 Altera Corporation Redundancy circuitry for logic circuits
US6091258A (en) * 1997-02-05 2000-07-18 Altera Corporation Redundancy circuitry for logic circuits
WO1998053401A1 (en) 1997-05-23 1998-11-26 Altera Corporation Redundancy circuitry for programmable logic devices with interleaved input circuits
KR100252053B1 (ko) * 1997-12-04 2000-05-01 윤종용 칼럼 방향의 데이터 입출력선을 가지는 반도체메모리장치와불량셀 구제회로 및 방법
US6201404B1 (en) 1998-07-14 2001-03-13 Altera Corporation Programmable logic device with redundant circuitry
US7340644B2 (en) 2002-12-02 2008-03-04 Marvell World Trade Ltd. Self-reparable semiconductor and method thereof
US7185225B2 (en) 2002-12-02 2007-02-27 Marvell World Trade Ltd. Self-reparable semiconductor and method thereof
US20060001669A1 (en) 2002-12-02 2006-01-05 Sehat Sutardja Self-reparable semiconductor and method thereof
US6879207B1 (en) * 2003-12-18 2005-04-12 Nvidia Corporation Defect tolerant redundancy
US8718079B1 (en) 2010-06-07 2014-05-06 Marvell International Ltd. Physical layer devices for network switches

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4281398A (en) * 1980-02-12 1981-07-28 Mostek Corporation Block redundancy for memory array
JPS59142800A (ja) * 1983-02-04 1984-08-16 Fujitsu Ltd 半導体集積回路装置
JPS59144098A (ja) * 1983-02-08 1984-08-17 Fujitsu Ltd 半導体記憶装置

Also Published As

Publication number Publication date
EP0361404B1 (de) 1995-12-13
EP0361404A3 (de) 1991-09-11
JPH0289299A (ja) 1990-03-29
DE68925090D1 (de) 1996-01-25
EP0361404A2 (de) 1990-04-04

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: NEC ELECTRONICS CORP., KAWASAKI, KANAGAWA, JP

8339 Ceased/non-payment of the annual fee