DE3339253A1 - Cmos-inverter - Google Patents

Cmos-inverter

Info

Publication number
DE3339253A1
DE3339253A1 DE19833339253 DE3339253A DE3339253A1 DE 3339253 A1 DE3339253 A1 DE 3339253A1 DE 19833339253 DE19833339253 DE 19833339253 DE 3339253 A DE3339253 A DE 3339253A DE 3339253 A1 DE3339253 A1 DE 3339253A1
Authority
DE
Germany
Prior art keywords
fet
channel mos
normally
inverter
voltage
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
DE19833339253
Other languages
German (de)
English (en)
Inventor
Hartmut Dr.-Phys. 8013 Haar Schrenk
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Siemens AG
Siemens Corp
Original Assignee
Siemens AG
Siemens Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens AG, Siemens Corp filed Critical Siemens AG
Priority to DE19833339253 priority Critical patent/DE3339253A1/de
Priority to AT84111726T priority patent/ATE31855T1/de
Priority to DE8484111726T priority patent/DE3468600D1/de
Priority to EP84111726A priority patent/EP0140188B1/de
Priority to JP59225609A priority patent/JPS60111529A/ja
Publication of DE3339253A1 publication Critical patent/DE3339253A1/de
Priority to US06/908,311 priority patent/US4675544A/en
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
    • H03K19/018507—Interface arrangements
    • H03K19/018521—Interface arrangements of complementary type, e.g. CMOS
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
    • H03K19/0944—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET or insulated gate field-effect transistors, i.e. IGFET
    • H03K19/0948—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET or insulated gate field-effect transistors, i.e. IGFET using CMOS or complementary insulated gate field-effect transistors
    • H03K19/09482—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET or insulated gate field-effect transistors, i.e. IGFET using CMOS or complementary insulated gate field-effect transistors using a combination of enhancement and depletion transistors
    • H03K19/09485—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET or insulated gate field-effect transistors, i.e. IGFET using CMOS or complementary insulated gate field-effect transistors using a combination of enhancement and depletion transistors with active depletion transistors

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Power Engineering (AREA)
  • Electronic Switches (AREA)
  • Logic Circuits (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Control Of Motors That Do Not Use Commutators (AREA)
DE19833339253 1983-10-28 1983-10-28 Cmos-inverter Withdrawn DE3339253A1 (de)

Priority Applications (6)

Application Number Priority Date Filing Date Title
DE19833339253 DE3339253A1 (de) 1983-10-28 1983-10-28 Cmos-inverter
AT84111726T ATE31855T1 (de) 1983-10-28 1984-10-01 Cmos-inverter.
DE8484111726T DE3468600D1 (de) 1983-10-28 1984-10-01 C-mos inverter
EP84111726A EP0140188B1 (de) 1983-10-28 1984-10-01 CMOS-Inverter
JP59225609A JPS60111529A (ja) 1983-10-28 1984-10-26 Ｃｍｏｓインバータ
US06/908,311 US4675544A (en) 1983-10-28 1986-09-17 CMOS-inverter

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE19833339253 DE3339253A1 (de) 1983-10-28 1983-10-28 Cmos-inverter

Publications (1)

Publication Number Publication Date
DE3339253A1 true DE3339253A1 (de) 1985-05-09

Family

ID=6213021

Family Applications (2)

Application Number Title Priority Date Filing Date
DE19833339253 Withdrawn DE3339253A1 (de) 1983-10-28 1983-10-28 Cmos-inverter
DE8484111726T Expired DE3468600D1 (de) 1983-10-28 1984-10-01 C-mos inverter

Family Applications After (1)

Application Number Title Priority Date Filing Date
DE8484111726T Expired DE3468600D1 (de) 1983-10-28 1984-10-01 C-mos inverter

Country Status (5)

Country Link
US (1) US4675544A (enExample)
EP (1) EP0140188B1 (enExample)
JP (1) JPS60111529A (enExample)
AT (1) ATE31855T1 (enExample)
DE (2) DE3339253A1 (enExample)

Families Citing this family (41)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4656373A (en) * 1984-11-26 1987-04-07 Rca Corporation High-speed voltage level shift circuit
GB2192105A (en) * 1986-06-25 1987-12-31 Philips Nv Cmos-input circuit
US4709162A (en) * 1986-09-18 1987-11-24 International Business Machines Corporation Off-chip driver circuits
US4825106A (en) * 1987-04-08 1989-04-25 Ncr Corporation MOS no-leak circuit
NL8800234A (nl) * 1988-02-01 1989-09-01 Philips Nv Geintegreerde schakeling met logische circuits en ten minste een push-pull-trap.
JPH0379121A (ja) * 1989-08-23 1991-04-04 Hitachi Ltd 半導体集積回路装置
EP0439149B1 (en) * 1990-01-23 1996-03-27 Nec Corporation Semiconductor digital circuits
US5128560A (en) * 1991-03-22 1992-07-07 Micron Technology, Inc. Boosted supply output driver circuit for driving an all N-channel output stage
US5359243A (en) * 1993-04-16 1994-10-25 Altera Corporation Fast TTL to CMOS level converting buffer with low standby power
JPH0878433A (ja) * 1994-08-31 1996-03-22 Nec Corp 半導体装置
JP3693369B2 (ja) * 1994-08-31 2005-09-07 株式会社 沖マイクロデザイン 不揮発性メモリ
US5852370A (en) * 1994-12-22 1998-12-22 Texas Instruments Incorporated Integrated circuits for low power dissipation in signaling between different-voltage on chip regions
JP3662326B2 (ja) * 1996-01-09 2005-06-22 株式会社ルネサステクノロジ レベル変換回路
US6198330B1 (en) * 1999-12-07 2001-03-06 Analog Devices, Inc. Adaptive-load inverters and methods
JP2002190723A (ja) * 2000-12-20 2002-07-05 Nippon Precision Circuits Inc 発振制御回路
US6870895B2 (en) * 2002-12-19 2005-03-22 Semiconductor Energy Laboratory Co., Ltd. Shift register and driving method thereof
US8447077B2 (en) 2006-09-11 2013-05-21 Validity Sensors, Inc. Method and apparatus for fingerprint motion tracking using an in-line array
WO2006041780A1 (en) 2004-10-04 2006-04-20 Validity Sensors, Inc. Fingerprint sensing assemblies comprising a substrate
JP4772542B2 (ja) * 2006-03-15 2011-09-14 株式会社東芝 電力変換装置
US8116540B2 (en) 2008-04-04 2012-02-14 Validity Sensors, Inc. Apparatus and method for reducing noise in fingerprint sensing circuits
WO2010036445A1 (en) 2008-07-22 2010-04-01 Validity Sensors, Inc. System, device and method for securing a device component
US8600122B2 (en) 2009-01-15 2013-12-03 Validity Sensors, Inc. Apparatus and method for culling substantially redundant data in fingerprint sensing circuits
US8278946B2 (en) 2009-01-15 2012-10-02 Validity Sensors, Inc. Apparatus and method for detecting finger activity on a fingerprint sensor
US20100176892A1 (en) * 2009-01-15 2010-07-15 Validity Sensors, Inc. Ultra Low Power Oscillator
JP5468882B2 (ja) * 2009-07-03 2014-04-09 セイコーインスツル株式会社 Ｃｍｏｓ入力バッファ回路
JP5603479B2 (ja) * 2009-07-03 2014-10-08 セイコーインスツル株式会社 Ｃｍｏｓ入力バッファ回路
US9336428B2 (en) 2009-10-30 2016-05-10 Synaptics Incorporated Integrated fingerprint sensor and display
US9666635B2 (en) 2010-02-19 2017-05-30 Synaptics Incorporated Fingerprint sensing circuit
US8716613B2 (en) 2010-03-02 2014-05-06 Synaptics Incoporated Apparatus and method for electrostatic discharge protection
US9001040B2 (en) 2010-06-02 2015-04-07 Synaptics Incorporated Integrated fingerprint sensor and navigation device
US8538097B2 (en) 2011-01-26 2013-09-17 Validity Sensors, Inc. User input utilizing dual line scanner apparatus and method
US8594393B2 (en) 2011-01-26 2013-11-26 Validity Sensors System for and method of image reconstruction with dual line scanner using line counts
US9195877B2 (en) 2011-12-23 2015-11-24 Synaptics Incorporated Methods and devices for capacitive image sensing
US9137438B2 (en) 2012-03-27 2015-09-15 Synaptics Incorporated Biometric object sensor and method
US9251329B2 (en) 2012-03-27 2016-02-02 Synaptics Incorporated Button depress wakeup and wakeup strategy
US9600709B2 (en) 2012-03-28 2017-03-21 Synaptics Incorporated Methods and systems for enrolling biometric data
KR20140028601A (ko) 2012-08-29 2014-03-10 에스케이하이닉스 주식회사 입출력센스앰프
US9143078B2 (en) 2012-11-29 2015-09-22 Infineon Technologies Ag Power inverter including SiC JFETs
US9665762B2 (en) 2013-01-11 2017-05-30 Synaptics Incorporated Tiered wakeup strategy
USD776664S1 (en) * 2015-05-20 2017-01-17 Chaya Coleena Hendrick Smart card
US11626864B1 (en) * 2021-12-08 2023-04-11 Macronix International Co., Ltd. Level shift circuit

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3678293A (en) * 1971-01-08 1972-07-18 Gen Instrument Corp Self-biasing inverter
JPS5318377A (en) * 1976-08-03 1978-02-20 Toshiba Corp Logical operation circuit
US4216390A (en) * 1978-10-04 1980-08-05 Rca Corporation Level shift circuit
EP0048922B1 (en) * 1980-09-26 1986-04-23 Kabushiki Kaisha Toshiba Dynamic signal generation circuit
JPS5891680A (ja) * 1981-11-26 1983-05-31 Fujitsu Ltd 半導体装置
US4469959A (en) * 1982-03-15 1984-09-04 Motorola, Inc. Input buffer
JPS5949020A (ja) * 1982-09-13 1984-03-21 Toshiba Corp 論理回路
US4501978A (en) * 1982-11-24 1985-02-26 Rca Corporation Level shift interface circuit
JPS59134918A (ja) * 1983-01-24 1984-08-02 Toshiba Corp ラツチ回路
US4508983A (en) * 1983-02-10 1985-04-02 Motorola, Inc. MOS Analog switch driven by complementary, minimally skewed clock signals
US4555642A (en) * 1983-09-22 1985-11-26 Standard Microsystems Corporation Low power CMOS input buffer circuit
US4563595A (en) * 1983-10-27 1986-01-07 National Semiconductor Corporation CMOS Schmitt trigger circuit for TTL logic levels

Also Published As

Publication number Publication date
EP0140188B1 (de) 1988-01-07
ATE31855T1 (de) 1988-01-15
DE3468600D1 (de) 1988-02-11
JPS60111529A (ja) 1985-06-18
EP0140188A3 (enExample) 1985-06-05
EP0140188A2 (de) 1985-05-08
US4675544A (en) 1987-06-23

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Legal Events

Date Code Title Description
8139 Disposal/non-payment of the annual fee