DE3320424A1 - Halbleiterelement - Google Patents
HalbleiterelementInfo
- Publication number
- DE3320424A1 DE3320424A1 DE19833320424 DE3320424A DE3320424A1 DE 3320424 A1 DE3320424 A1 DE 3320424A1 DE 19833320424 DE19833320424 DE 19833320424 DE 3320424 A DE3320424 A DE 3320424A DE 3320424 A1 DE3320424 A1 DE 3320424A1
- Authority
- DE
- Germany
- Prior art keywords
- impurity diffusion
- insulating film
- film
- oxide film
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P54/00—Cutting or separating of wafers, substrates or parts of devices
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
- H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
- H10D62/112—Constructional design considerations for preventing surface leakage or controlling electric field concentration for preventing surface leakage due to surface inversion layers, e.g. by using channel stoppers
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W20/00—Interconnections in chips, wafers or substrates
- H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
Landscapes
- Semiconductor Integrated Circuits (AREA)
- Dicing (AREA)
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57100252A JPS58216439A (ja) | 1982-06-09 | 1982-06-09 | 半導体装置 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| DE3320424A1 true DE3320424A1 (de) | 1983-12-15 |
| DE3320424C2 DE3320424C2 (https=) | 1990-10-31 |
Family
ID=14269027
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| DE19833320424 Granted DE3320424A1 (de) | 1982-06-09 | 1983-06-06 | Halbleiterelement |
Country Status (2)
| Country | Link |
|---|---|
| JP (1) | JPS58216439A (https=) |
| DE (1) | DE3320424A1 (https=) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE3817918A1 (de) * | 1987-05-27 | 1988-12-08 | Mitsubishi Electric Corp | Halbleiterspeichereinrichtung |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP5543786B2 (ja) * | 2008-01-09 | 2014-07-09 | ローム株式会社 | 半導体装置及びその製造方法 |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3247428A (en) * | 1961-09-29 | 1966-04-19 | Ibm | Coated objects and methods of providing the protective coverings therefor |
| US3967310A (en) * | 1968-10-09 | 1976-06-29 | Hitachi, Ltd. | Semiconductor device having controlled surface charges by passivation films formed thereon |
| US3967364A (en) * | 1973-10-12 | 1976-07-06 | Hitachi, Ltd. | Method of manufacturing semiconductor devices |
| US4151607A (en) * | 1976-07-05 | 1979-04-24 | Hitachi, Ltd. | Semiconductor memory device |
-
1982
- 1982-06-09 JP JP57100252A patent/JPS58216439A/ja active Pending
-
1983
- 1983-06-06 DE DE19833320424 patent/DE3320424A1/de active Granted
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3247428A (en) * | 1961-09-29 | 1966-04-19 | Ibm | Coated objects and methods of providing the protective coverings therefor |
| US3967310A (en) * | 1968-10-09 | 1976-06-29 | Hitachi, Ltd. | Semiconductor device having controlled surface charges by passivation films formed thereon |
| US3967364A (en) * | 1973-10-12 | 1976-07-06 | Hitachi, Ltd. | Method of manufacturing semiconductor devices |
| US4151607A (en) * | 1976-07-05 | 1979-04-24 | Hitachi, Ltd. | Semiconductor memory device |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE3817918A1 (de) * | 1987-05-27 | 1988-12-08 | Mitsubishi Electric Corp | Halbleiterspeichereinrichtung |
Also Published As
| Publication number | Publication date |
|---|---|
| DE3320424C2 (https=) | 1990-10-31 |
| JPS58216439A (ja) | 1983-12-16 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| DE69315239T2 (de) | VDMOS-Transistor mit verbesserter Durchbruchsspannungscharakteristik | |
| DE69330603T2 (de) | Verfahren zur Metallisierung und Verbindung bei der Herstellung von Leistungshalbleiterbauelementen | |
| DE2930630C2 (de) | Halbleiterbauelement sowie Verfahren zu seiner Herstellung | |
| DE3888937T2 (de) | Verfahren zum Herstellen von integrierten Schaltungen mit FET. | |
| DE69015666T2 (de) | MOSFET-Transistor mit nicht-gleichmässiger Schwellspannung im Kanalbereich. | |
| DE2916364C2 (https=) | ||
| DE69122043T2 (de) | Vertikaler SOI-Feldeffekttransistor und dessen Herstellungsprozess | |
| DE3588050T2 (de) | Halbleiterspeichervorrichtung und Verfahren zu deren Herstellung. | |
| DE4220497A1 (de) | Halbleiterspeicherbauelement und verfahren zu dessen herstellung | |
| DE69505348T2 (de) | Hochspannungs-MOSFET mit Feldplatten-Elektrode und Verfahren zur Herstellung | |
| DE69214339T2 (de) | Struktur und Verfahren für die Bildung selbstjustierender Kontakte | |
| DE19638684A1 (de) | Halbleitervorrichtung mit einem Kontaktloch | |
| DE3889610T2 (de) | Halbleiteranordnung mit einem Trench-Bipolartransistor. | |
| DE2726003A1 (de) | Verfahren zur herstellung von mis- bauelementen mit versetztem gate | |
| DE3603470A1 (de) | Verfahren zur herstellung von feldeffektbauelementen auf einem siliziumsubstrat | |
| DE2928923A1 (de) | Halbleitervorrichtung | |
| EP0038994A2 (de) | Kontakt für MIS-Halbleiterbauelement und Verfahren zu seiner Herstellung | |
| DE112022000700T5 (de) | Halbleiterbauteil | |
| DE3426306A1 (de) | Mos-transistor und verfahren zu seiner herstellung | |
| DE2453279C3 (de) | Halbleiteranordnung | |
| DE3543937C2 (https=) | ||
| DE3688757T2 (de) | Verfahren zur Herstellung von Halbleiteranordnungen mit Isolationszonen. | |
| DE69226569T2 (de) | Selbstjustierender Polysilizium-T-Gatekontakt | |
| DE2111633A1 (de) | Verfahren zur Herstellung eines Oberflaechen-Feldeffekt-Transistors | |
| DE68925092T2 (de) | MOS-Feldeffekttransistor |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| OM8 | Search report available as to paragraph 43 lit. 1 sentence 1 patent law | ||
| 8110 | Request for examination paragraph 44 | ||
| D2 | Grant after examination | ||
| 8363 | Opposition against the patent | ||
| 8325 | Change of the main classification |
Ipc: H01L 21/78 |
|
| 8365 | Fully valid after opposition proceedings | ||
| 8320 | Willingness to grant licences declared (paragraph 23) |