DE3022726A1 - Schichtanordnung zur passivierung, die ueber dem ort einer maske von selbst ausgerichtet ist, und verfahren zum erzeugen derselben - Google Patents

Schichtanordnung zur passivierung, die ueber dem ort einer maske von selbst ausgerichtet ist, und verfahren zum erzeugen derselben

Info

Publication number
DE3022726A1
DE3022726A1 DE19803022726 DE3022726A DE3022726A1 DE 3022726 A1 DE3022726 A1 DE 3022726A1 DE 19803022726 DE19803022726 DE 19803022726 DE 3022726 A DE3022726 A DE 3022726A DE 3022726 A1 DE3022726 A1 DE 3022726A1
Authority
DE
Germany
Prior art keywords
layer
passivation
silicon
mask
metal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
DE19803022726
Other languages
German (de)
English (en)
Inventor
Andre Peyre-Lavigne
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Thales SA
Original Assignee
Thomson CSF SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Thomson CSF SA filed Critical Thomson CSF SA
Publication of DE3022726A1 publication Critical patent/DE3022726A1/de
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H10W74/01—
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
    • H01L23/298—Semiconductor material, e.g. amorphous silicon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157—Partial encapsulation or coating
    • H01L23/3171—Partial encapsulation or coating the coating being directly applied to the semiconductor body, e.g. passivation layer
    • H10P14/60—
    • H10P76/40—
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/01—Bipolar transistors-ion implantation
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/958—Passivation layer

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Formation Of Insulating Films (AREA)
  • Electrodes Of Semiconductors (AREA)
DE19803022726 1979-06-19 1980-06-18 Schichtanordnung zur passivierung, die ueber dem ort einer maske von selbst ausgerichtet ist, und verfahren zum erzeugen derselben Withdrawn DE3022726A1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR7915661A FR2459551A1 (fr) 1979-06-19 1979-06-19 Procede et structure de passivation a autoalignement sur l'emplacement d'un masque

Publications (1)

Publication Number Publication Date
DE3022726A1 true DE3022726A1 (de) 1981-01-22

Family

ID=9226786

Family Applications (1)

Application Number Title Priority Date Filing Date
DE19803022726 Withdrawn DE3022726A1 (de) 1979-06-19 1980-06-18 Schichtanordnung zur passivierung, die ueber dem ort einer maske von selbst ausgerichtet ist, und verfahren zum erzeugen derselben

Country Status (3)

Country Link
US (1) US4332837A (enExample)
DE (1) DE3022726A1 (enExample)
FR (1) FR2459551A1 (enExample)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0051488B1 (en) * 1980-11-06 1985-01-30 Kabushiki Kaisha Toshiba Method for manufacturing a semiconductor device
FR2518810A1 (fr) 1981-12-23 1983-06-24 Morin Francois Procede de fabrication de transistors en couches minces en silicium sur substrat isolant
US4521952A (en) * 1982-12-02 1985-06-11 International Business Machines Corporation Method of making integrated circuits using metal silicide contacts
US5185179A (en) * 1988-10-11 1993-02-09 Semiconductor Energy Laboratory Co., Ltd. Plasma processing method and products thereof
JP2855919B2 (ja) * 1991-10-24 1999-02-10 日本電気株式会社 半導体装置およびその製造方法
US5387548A (en) * 1992-06-22 1995-02-07 Motorola, Inc. Method of forming an etched ohmic contact
JPH07218463A (ja) * 1994-02-04 1995-08-18 Figaro Eng Inc 金属酸化物表面へのシリカマスクの調製方法
DE4424420A1 (de) * 1994-07-12 1996-01-18 Telefunken Microelectron Kontaktierungsprozeß
US6221760B1 (en) * 1997-10-20 2001-04-24 Nec Corporation Semiconductor device having a silicide structure
JP5195186B2 (ja) * 2008-09-05 2013-05-08 三菱電機株式会社 半導体装置の製造方法

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
NL302322A (enExample) * 1963-02-08
DE1213921B (de) * 1964-08-25 1966-04-07 Bosch Gmbh Robert Verfahren zur Herstellung einer Halbleiteranordnung
DE1521529C3 (de) * 1965-06-15 1974-11-28 Telefunken Patentverwertungsgesellschaft Mbh, 7900 Ulm Verfahren zur Herstellung von feinen Strukturen auf einem Substrat
JPS6022497B2 (ja) * 1974-10-26 1985-06-03 ソニー株式会社 半導体装置
JPS6041458B2 (ja) * 1975-04-21 1985-09-17 ソニー株式会社 半導体装置の製造方法
FR2335951A1 (fr) * 1975-12-19 1977-07-15 Radiotechnique Compelec Dispositif semiconducteur a surface passivee et procede d'obtention de la structure de passivation
US4194934A (en) * 1977-05-23 1980-03-25 Varo Semiconductor, Inc. Method of passivating a semiconductor device utilizing dual polycrystalline layers
US4180596A (en) * 1977-06-30 1979-12-25 International Business Machines Corporation Method for providing a metal silicide layer on a substrate

Also Published As

Publication number Publication date
US4332837A (en) 1982-06-01
FR2459551A1 (fr) 1981-01-09
FR2459551B1 (enExample) 1983-04-29

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Legal Events

Date Code Title Description
8139 Disposal/non-payment of the annual fee