DE2754354A1 - Programmierbare logische baugruppenanordnung - Google Patents

Programmierbare logische baugruppenanordnung

Info

Publication number
DE2754354A1
DE2754354A1 DE19772754354 DE2754354A DE2754354A1 DE 2754354 A1 DE2754354 A1 DE 2754354A1 DE 19772754354 DE19772754354 DE 19772754354 DE 2754354 A DE2754354 A DE 2754354A DE 2754354 A1 DE2754354 A1 DE 2754354A1
Authority
DE
Germany
Prior art keywords
lines
matrix
layer
arrangement according
arrangement
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
DE19772754354
Other languages
German (de)
English (en)
Inventor
Keisuke Kataoka
Yoshi Sugiyama
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NTT Inc
Original Assignee
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from JP14944176A external-priority patent/JPS5373930A/ja
Priority claimed from JP3472677A external-priority patent/JPS53120345A/ja
Application filed by Nippon Telegraph and Telephone Corp filed Critical Nippon Telegraph and Telephone Corp
Publication of DE2754354A1 publication Critical patent/DE2754354A1/de
Ceased legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/90—Masterslice integrated circuits
    • H10D84/901—Masterslice integrated circuits comprising bipolar technology
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/525—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/525—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
    • H01L23/5256—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections comprising fuses, i.e. connections having their state changed from conductive to non-conductive
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17704—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns
    • H03K19/17708—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns using an AND matrix followed by an OR matrix, i.e. programmable logic arrays
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Mathematical Physics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Logic Circuits (AREA)
DE19772754354 1976-12-14 1977-12-07 Programmierbare logische baugruppenanordnung Ceased DE2754354A1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP14944176A JPS5373930A (en) 1976-12-14 1976-12-14 Programable logic array master chip
JP3472677A JPS53120345A (en) 1977-03-30 1977-03-30 Master chip of array logic

Publications (1)

Publication Number Publication Date
DE2754354A1 true DE2754354A1 (de) 1978-06-22

Family

ID=26373571

Family Applications (1)

Application Number Title Priority Date Filing Date
DE19772754354 Ceased DE2754354A1 (de) 1976-12-14 1977-12-07 Programmierbare logische baugruppenanordnung

Country Status (4)

Country Link
US (1) US4207556A (enExample)
DE (1) DE2754354A1 (enExample)
FR (1) FR2374817A1 (enExample)
GB (1) GB1600623A (enExample)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3223276A1 (de) * 1981-06-22 1983-01-05 Hitachi Microcomputer Engineering Ltd., Tokyo Integrierte halbleiterschaltung und verfahren zu ihrer herstellung

Families Citing this family (65)

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JPS558135A (en) * 1978-07-04 1980-01-21 Mamoru Tanaka Rewritable programable logic array
DE3066941D1 (en) * 1979-05-24 1984-04-19 Fujitsu Ltd Masterslice semiconductor device and method of producing it
JPS5843905B2 (ja) * 1979-07-31 1983-09-29 富士通株式会社 半導体集積回路の製造方法
US4314349A (en) * 1979-12-31 1982-02-02 Goodyear Aerospace Corporation Processing element for parallel array processors
FR2495834A1 (fr) * 1980-12-05 1982-06-11 Cii Honeywell Bull Dispositif a circuits integres de haute densite
US4495590A (en) * 1980-12-31 1985-01-22 International Business Machines Corporation PLA With time division multiplex feature for improved density
US4458163A (en) * 1981-07-20 1984-07-03 Texas Instruments Incorporated Programmable architecture logic
US4422072A (en) * 1981-07-30 1983-12-20 Signetics Corporation Field programmable logic array circuit
US4442508A (en) * 1981-08-05 1984-04-10 General Instrument Corporation Storage cells for use in two conductor data column storage logic arrays
US4494017A (en) * 1982-03-29 1985-01-15 International Business Machines Corporation Complementary decode circuit
US4504904A (en) * 1982-06-15 1985-03-12 International Business Machines Corporation Binary logic structure employing programmable logic arrays and useful in microword generation apparatus
US4661922A (en) * 1982-12-08 1987-04-28 American Telephone And Telegraph Company Programmed logic array with two-level control timing
US4525714A (en) * 1982-12-03 1985-06-25 Honeywell Information Systems Inc. Programmable logic array with test capability in the unprogrammed state
US4488230A (en) * 1982-12-08 1984-12-11 At&T Bell Laboratories Programmed logic array with external signals introduced between its AND plane and its OR plane
JPS6091722A (ja) * 1983-10-26 1985-05-23 Hitachi Ltd 半導体集積回路装置
USRE34363E (en) * 1984-03-12 1993-08-31 Xilinx, Inc. Configurable electrical circuit having configurable logic elements and configurable interconnects
US4609986A (en) * 1984-06-14 1986-09-02 Altera Corporation Programmable logic array device using EPROM technology
US4645953A (en) * 1984-07-03 1987-02-24 Monolithic Memories, Inc. Current source which saves power in programmable logic array circuitry
GB2168840A (en) * 1984-08-22 1986-06-25 Plessey Co Plc Customerisation of integrated logic devices
GB2167621B (en) * 1984-11-27 1988-03-02 Crystalate Electronics Programmed matrix device
US4697241A (en) * 1985-03-01 1987-09-29 Simulog, Inc. Hardware logic simulator
US4814646A (en) * 1985-03-22 1989-03-21 Monolithic Memories, Inc. Programmable logic array using emitter-coupled logic
US4742252A (en) * 1985-03-29 1988-05-03 Advanced Micro Devices, Inc. Multiple array customizable logic device
US5225719A (en) * 1985-03-29 1993-07-06 Advanced Micro Devices, Inc. Family of multiple segmented programmable logic blocks interconnected by a high speed centralized switch matrix
US4763020B1 (en) * 1985-09-06 1997-07-08 Ricoh Kk Programmable logic device having plural programmable function cells
AU593281B2 (en) * 1985-09-11 1990-02-08 Motorola, Inc. Semi-conductor integrated circuit/systems
JPS62139198A (ja) * 1985-12-11 1987-06-22 Mitsubishi Electric Corp 半導体記憶装置
US5367208A (en) * 1986-09-19 1994-11-22 Actel Corporation Reconfigurable programmable interconnect architecture
US5341092A (en) * 1986-09-19 1994-08-23 Actel Corporation Testability architecture and techniques for programmable interconnect architecture
US5451887A (en) * 1986-09-19 1995-09-19 Actel Corporation Programmable logic module and architecture for field programmable gate array device
US5365165A (en) * 1986-09-19 1994-11-15 Actel Corporation Testability architecture and techniques for programmable interconnect architecture
US4758745B1 (en) * 1986-09-19 1994-11-15 Actel Corp User programmable integrated circuit interconnect architecture and test method
US4721868A (en) * 1986-09-23 1988-01-26 Advanced Micro Devices, Inc. IC input circuitry programmable for realizing multiple functions from a single input
USRE34444E (en) * 1988-01-13 1993-11-16 Xilinx, Inc. Programmable logic device
US5023606A (en) * 1988-01-13 1991-06-11 Plus Logic, Inc. Programmable logic device with ganged output pins
US4847612A (en) * 1988-01-13 1989-07-11 Plug Logic, Inc. Programmable logic device
JPH01278041A (ja) * 1988-04-30 1989-11-08 Hitachi Ltd 半導体集積回路装置
US4933576A (en) * 1988-05-13 1990-06-12 Fujitsu Limited Gate array device having macro cells for forming master and slave cells of master-slave flip-flop circuit
US4937475B1 (en) * 1988-09-19 1994-03-29 Massachusetts Inst Technology Laser programmable integrated circuit
US4910418A (en) * 1988-12-29 1990-03-20 Gazelle Microcircuits, Inc. Semiconductor fuse programmable array structure
US4967107A (en) * 1989-05-12 1990-10-30 Plus Logic, Inc. Programmable logic expander
US5028821A (en) * 1990-03-01 1991-07-02 Plus Logic, Inc. Programmable logic device with programmable inverters at input/output pads
US5322812A (en) * 1991-03-20 1994-06-21 Crosspoint Solutions, Inc. Improved method of fabricating antifuses in an integrated circuit device and resulting structure
US5294846A (en) * 1992-08-17 1994-03-15 Paivinen John O Method and apparatus for programming anti-fuse devices
JP3922653B2 (ja) * 1993-03-17 2007-05-30 ゲイトフィールド・コーポレイション ランダムアクセスメモリ（ｒａｍ）ベースのコンフィギュラブルアレイ
US5457410A (en) * 1993-08-03 1995-10-10 Btr, Inc. Architecture and interconnect scheme for programmable logic circuits
US5742179A (en) * 1994-01-27 1998-04-21 Dyna Logic Corporation High speed programmable logic architecture
US5424655A (en) * 1994-05-20 1995-06-13 Quicklogic Corporation Programmable application specific integrated circuit employing antifuses and methods therefor
US5495181A (en) * 1994-12-01 1996-02-27 Quicklogic Corporation Integrated circuit facilitating simultaneous programming of multiple antifuses
US5552720A (en) * 1994-12-01 1996-09-03 Quicklogic Corporation Method for simultaneous programming of multiple antifuses
US6034547A (en) * 1996-09-04 2000-03-07 Advantage Logic, Inc. Method and apparatus for universal program controlled bus
US6624658B2 (en) * 1999-02-04 2003-09-23 Advantage Logic, Inc. Method and apparatus for universal program controlled bus architecture
JP3420694B2 (ja) * 1996-12-27 2003-06-30 株式会社東芝 スタンダードセル方式の集積回路
US7112994B2 (en) 2002-07-08 2006-09-26 Viciciv Technology Three dimensional integrated circuits
US6992503B2 (en) 2002-07-08 2006-01-31 Viciciv Technology Programmable devices with convertibility to customizable devices
US8643162B2 (en) 2007-11-19 2014-02-04 Raminda Udaya Madurawe Pads and pin-outs in three dimensional integrated circuits
JP2004221231A (ja) * 2003-01-14 2004-08-05 Nec Electronics Corp レイアウトパターン生成のための装置と方法、及びそれを用いた半導体装置の製造方法
US7255437B2 (en) * 2003-10-09 2007-08-14 Howell Thomas A Eyeglasses with activity monitoring
US6897543B1 (en) 2003-08-22 2005-05-24 Altera Corporation Electrically-programmable integrated circuit antifuses
US7030651B2 (en) 2003-12-04 2006-04-18 Viciciv Technology Programmable structured arrays
US7157782B1 (en) 2004-02-17 2007-01-02 Altera Corporation Electrically-programmable transistor antifuses
WO2008112052A1 (en) * 2007-02-05 2008-09-18 Process Engineering And Manufacturing Turn-around scrubber
US7629812B2 (en) * 2007-08-03 2009-12-08 Dsm Solutions, Inc. Switching circuits and methods for programmable logic devices
US8661394B1 (en) 2008-09-24 2014-02-25 Iowa State University Research Foundation, Inc. Depth-optimal mapping of logic chains in reconfigurable fabrics
US8438522B1 (en) 2008-09-24 2013-05-07 Iowa State University Research Foundation, Inc. Logic element architecture for generic logic chains in programmable devices

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5033754B1 (enExample) * 1971-02-24 1975-11-01
JPS5435474B2 (enExample) * 1973-03-26 1979-11-02
US3983538A (en) * 1974-05-01 1976-09-28 International Business Machines Corporation Universal LSI array logic modules with integral storage array and variable autonomous sequencing
IT1042852B (it) * 1974-09-30 1980-01-30 Siemens Ag Disposizione di circuiti logici integrata e programmabile

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3223276A1 (de) * 1981-06-22 1983-01-05 Hitachi Microcomputer Engineering Ltd., Tokyo Integrierte halbleiterschaltung und verfahren zu ihrer herstellung

Also Published As

Publication number Publication date
GB1600623A (en) 1981-10-21
US4207556A (en) 1980-06-10
FR2374817B1 (enExample) 1983-01-21
FR2374817A1 (fr) 1978-07-13

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