DE2438256A1 - Verfahren zum herstellen einer monolithischen halbleiterverbundanordnung - Google Patents

Verfahren zum herstellen einer monolithischen halbleiterverbundanordnung

Info

Publication number
DE2438256A1
DE2438256A1 DE2438256A DE2438256A DE2438256A1 DE 2438256 A1 DE2438256 A1 DE 2438256A1 DE 2438256 A DE2438256 A DE 2438256A DE 2438256 A DE2438256 A DE 2438256A DE 2438256 A1 DE2438256 A1 DE 2438256A1
Authority
DE
Germany
Prior art keywords
silicon
trench
etching mask
mask
silicon nitride
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
DE2438256A
Other languages
German (de)
English (en)
Inventor
Helmuth Dipl Phys Dr Murrmann
Ulrich Dr Phil Schwabe
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Siemens Corp
Original Assignee
Siemens Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens Corp filed Critical Siemens Corp
Priority to DE2438256A priority Critical patent/DE2438256A1/de
Priority to GB28824/75A priority patent/GB1504636A/en
Priority to FR7523978A priority patent/FR2281646A1/fr
Priority to US05/601,222 priority patent/US4014714A/en
Priority to IT26116/75A priority patent/IT1040488B/it
Priority to CA233,016A priority patent/CA1062589A/en
Priority to JP9656775A priority patent/JPS5512736B2/ja
Publication of DE2438256A1 publication Critical patent/DE2438256A1/de
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/61—Formation of materials, e.g. in the shape of layers or pillars of insulating materials using masks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P95/00—Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H10W10/011—Manufacture or treatment of isolation regions comprising dielectric materials
    • H10W10/012—Manufacture or treatment of isolation regions comprising dielectric materials using local oxidation of silicon [LOCOS]
    • H10W10/0121—Manufacture or treatment of isolation regions comprising dielectric materials using local oxidation of silicon [LOCOS] in regions recessed from the surface, e.g. in trenches or grooves
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/13—Isolation regions comprising dielectric materials formed using local oxidation of silicon [LOCOS], e.g. sealed interface localised oxidation [SILO] or side-wall mask isolation [SWAMI]
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/106—Masks, special
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/114—Nitrides of silicon
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/117—Oxidation, selective
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/942—Masking
    • Y10S438/944—Shadow

Landscapes

  • Element Separation (AREA)
  • Semiconductor Integrated Circuits (AREA)
DE2438256A 1974-08-08 1974-08-08 Verfahren zum herstellen einer monolithischen halbleiterverbundanordnung Pending DE2438256A1 (de)

Priority Applications (7)

Application Number Priority Date Filing Date Title
DE2438256A DE2438256A1 (de) 1974-08-08 1974-08-08 Verfahren zum herstellen einer monolithischen halbleiterverbundanordnung
GB28824/75A GB1504636A (en) 1974-08-08 1975-07-09 Monolithic compound semiconductor arrangements
FR7523978A FR2281646A1 (fr) 1974-08-08 1975-07-31 Procede pour fabriquer un dispositif composite monolithique a semiconducteurs
US05/601,222 US4014714A (en) 1974-08-08 1975-08-01 Method of producing a monolithic semiconductor device
IT26116/75A IT1040488B (it) 1974-08-08 1975-08-05 Procedimento per fabbricare un di spositivo composito monolitico a semiconduttori
CA233,016A CA1062589A (en) 1974-08-08 1975-08-07 Method of manufacturing a monolithic semiconductor compound device
JP9656775A JPS5512736B2 (enExample) 1974-08-08 1975-08-08

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE2438256A DE2438256A1 (de) 1974-08-08 1974-08-08 Verfahren zum herstellen einer monolithischen halbleiterverbundanordnung

Publications (1)

Publication Number Publication Date
DE2438256A1 true DE2438256A1 (de) 1976-02-19

Family

ID=5922779

Family Applications (1)

Application Number Title Priority Date Filing Date
DE2438256A Pending DE2438256A1 (de) 1974-08-08 1974-08-08 Verfahren zum herstellen einer monolithischen halbleiterverbundanordnung

Country Status (7)

Country Link
US (1) US4014714A (enExample)
JP (1) JPS5512736B2 (enExample)
CA (1) CA1062589A (enExample)
DE (1) DE2438256A1 (enExample)
FR (1) FR2281646A1 (enExample)
GB (1) GB1504636A (enExample)
IT (1) IT1040488B (enExample)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4143455A (en) * 1976-03-11 1979-03-13 Siemens Aktiengesellschaft Method of producing a semiconductor component
JPS5429573A (en) * 1977-08-10 1979-03-05 Hitachi Ltd Fine machining method of semiconductor
US4219369A (en) * 1977-09-30 1980-08-26 Hitachi, Ltd. Method of making semiconductor integrated circuit device
US4306916A (en) * 1979-09-20 1981-12-22 American Microsystems, Inc. CMOS P-Well selective implant method
JPS5667851U (enExample) * 1979-10-31 1981-06-05
JPS5673446A (en) * 1979-11-21 1981-06-18 Chiyou Lsi Gijutsu Kenkyu Kumiai Manufacture of semiconductor device
NL187328C (nl) * 1980-12-23 1991-08-16 Philips Nv Werkwijze ter vervaardiging van een halfgeleiderinrichting.
US4472873A (en) * 1981-10-22 1984-09-25 Fairchild Camera And Instrument Corporation Method for forming submicron bipolar transistors without epitaxial growth and the resulting structure
JPS5934496U (ja) * 1982-08-26 1984-03-03 株式会社明電舎 インバ−タの保護回路
EP1347505A3 (en) * 1991-02-15 2004-10-20 Canon Kabushiki Kaisha Method of preparing semiconductor member using an etching solution
US5364810A (en) * 1992-07-28 1994-11-15 Motorola, Inc. Methods of forming a vertical field-effect transistor and a semiconductor memory cell
US20060108641A1 (en) * 2004-11-19 2006-05-25 Taiwan Semiconductor Manufacturing Company, Ltd. Device having a laterally graded well structure and a method for its manufacture

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
NL170348C (nl) * 1970-07-10 1982-10-18 Philips Nv Werkwijze voor het vervaardigen van een halfgeleiderinrichting, waarbij op een oppervlak van een halfgeleiderlichaam een tegen dotering en tegen thermische oxydatie maskerend masker wordt aangebracht, de door de vensters in het masker vrijgelaten delen van het oppervlak worden onderworpen aan een etsbehandeling voor het vormen van verdiepingen en het halfgeleiderlichaam met het masker wordt onderworpen aan een thermische oxydatiebehandeling voor het vormen van een oxydepatroon dat de verdiepingen althans ten dele opvult.
NL173110C (nl) * 1971-03-17 1983-12-01 Philips Nv Werkwijze ter vervaardiging van een halfgeleiderinrichting, waarbij op een oppervlak van een halfgeleiderlichaam een uit ten minste twee deellagen van verschillend materiaal samengestelde maskeringslaag wordt aangebracht.
US3725150A (en) * 1971-10-29 1973-04-03 Motorola Inc Process for making a fine geometry, self-aligned device structure
US3808058A (en) * 1972-08-17 1974-04-30 Bell Telephone Labor Inc Fabrication of mesa diode with channel guard

Also Published As

Publication number Publication date
JPS5141976A (enExample) 1976-04-08
CA1062589A (en) 1979-09-18
JPS5512736B2 (enExample) 1980-04-03
US4014714A (en) 1977-03-29
IT1040488B (it) 1979-12-20
GB1504636A (en) 1978-03-22
FR2281646A1 (fr) 1976-03-05

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Legal Events

Date Code Title Description
OHW Rejection