JPS5512736B2 - - Google Patents
Info
- Publication number
- JPS5512736B2 JPS5512736B2 JP9656775A JP9656775A JPS5512736B2 JP S5512736 B2 JPS5512736 B2 JP S5512736B2 JP 9656775 A JP9656775 A JP 9656775A JP 9656775 A JP9656775 A JP 9656775A JP S5512736 B2 JPS5512736 B2 JP S5512736B2
- Authority
- JP
- Japan
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/32—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers using masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
- H01L21/76205—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO in a region being recessed from the surface, e.g. in a recess, groove, tub or trench region
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S148/00—Metal treatment
- Y10S148/106—Masks, special
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S148/00—Metal treatment
- Y10S148/114—Nitrides of silicon
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S148/00—Metal treatment
- Y10S148/117—Oxidation, selective
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S438/00—Semiconductor device manufacturing: process
- Y10S438/942—Masking
- Y10S438/944—Shadow
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Element Separation (AREA)
- Semiconductor Integrated Circuits (AREA)
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| DE2438256A DE2438256A1 (de) | 1974-08-08 | 1974-08-08 | Verfahren zum herstellen einer monolithischen halbleiterverbundanordnung |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5141976A JPS5141976A (ja) | 1976-04-08 |
| JPS5512736B2 true JPS5512736B2 (ja) | 1980-04-03 |
Family
ID=5922779
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9656775A Expired JPS5512736B2 (ja) | 1974-08-08 | 1975-08-08 |
Country Status (7)
| Country | Link |
|---|---|
| US (1) | US4014714A (ja) |
| JP (1) | JPS5512736B2 (ja) |
| CA (1) | CA1062589A (ja) |
| DE (1) | DE2438256A1 (ja) |
| FR (1) | FR2281646A1 (ja) |
| GB (1) | GB1504636A (ja) |
| IT (1) | IT1040488B (ja) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5934496U (ja) * | 1982-08-26 | 1984-03-03 | 株式会社明電舎 | インバ−タの保護回路 |
Families Citing this family (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4143455A (en) * | 1976-03-11 | 1979-03-13 | Siemens Aktiengesellschaft | Method of producing a semiconductor component |
| JPS5429573A (en) * | 1977-08-10 | 1979-03-05 | Hitachi Ltd | Fine machining method of semiconductor |
| US4219369A (en) * | 1977-09-30 | 1980-08-26 | Hitachi, Ltd. | Method of making semiconductor integrated circuit device |
| US4306916A (en) * | 1979-09-20 | 1981-12-22 | American Microsystems, Inc. | CMOS P-Well selective implant method |
| JPS5667851U (ja) * | 1979-10-31 | 1981-06-05 | ||
| JPS5673446A (en) * | 1979-11-21 | 1981-06-18 | Chiyou Lsi Gijutsu Kenkyu Kumiai | Manufacture of semiconductor device |
| NL187328C (nl) * | 1980-12-23 | 1991-08-16 | Philips Nv | Werkwijze ter vervaardiging van een halfgeleiderinrichting. |
| US4472873A (en) * | 1981-10-22 | 1984-09-25 | Fairchild Camera And Instrument Corporation | Method for forming submicron bipolar transistors without epitaxial growth and the resulting structure |
| US5767020A (en) * | 1991-02-15 | 1998-06-16 | Canon Kabushiki Kaisha | Etching solution for etching porous silicon, etching method using the etching solution and method of preparing semiconductor member using the etching solution |
| US5364810A (en) * | 1992-07-28 | 1994-11-15 | Motorola, Inc. | Methods of forming a vertical field-effect transistor and a semiconductor memory cell |
| US20060108641A1 (en) * | 2004-11-19 | 2006-05-25 | Taiwan Semiconductor Manufacturing Company, Ltd. | Device having a laterally graded well structure and a method for its manufacture |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| NL170348C (nl) * | 1970-07-10 | 1982-10-18 | Philips Nv | Werkwijze voor het vervaardigen van een halfgeleiderinrichting, waarbij op een oppervlak van een halfgeleiderlichaam een tegen dotering en tegen thermische oxydatie maskerend masker wordt aangebracht, de door de vensters in het masker vrijgelaten delen van het oppervlak worden onderworpen aan een etsbehandeling voor het vormen van verdiepingen en het halfgeleiderlichaam met het masker wordt onderworpen aan een thermische oxydatiebehandeling voor het vormen van een oxydepatroon dat de verdiepingen althans ten dele opvult. |
| NL173110C (nl) * | 1971-03-17 | 1983-12-01 | Philips Nv | Werkwijze ter vervaardiging van een halfgeleiderinrichting, waarbij op een oppervlak van een halfgeleiderlichaam een uit ten minste twee deellagen van verschillend materiaal samengestelde maskeringslaag wordt aangebracht. |
| US3725150A (en) * | 1971-10-29 | 1973-04-03 | Motorola Inc | Process for making a fine geometry, self-aligned device structure |
| US3808058A (en) * | 1972-08-17 | 1974-04-30 | Bell Telephone Labor Inc | Fabrication of mesa diode with channel guard |
-
1974
- 1974-08-08 DE DE2438256A patent/DE2438256A1/de active Pending
-
1975
- 1975-07-09 GB GB28824/75A patent/GB1504636A/en not_active Expired
- 1975-07-31 FR FR7523978A patent/FR2281646A1/fr not_active Withdrawn
- 1975-08-01 US US05/601,222 patent/US4014714A/en not_active Expired - Lifetime
- 1975-08-05 IT IT26116/75A patent/IT1040488B/it active
- 1975-08-07 CA CA233,016A patent/CA1062589A/en not_active Expired
- 1975-08-08 JP JP9656775A patent/JPS5512736B2/ja not_active Expired
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5934496U (ja) * | 1982-08-26 | 1984-03-03 | 株式会社明電舎 | インバ−タの保護回路 |
Also Published As
| Publication number | Publication date |
|---|---|
| CA1062589A (en) | 1979-09-18 |
| FR2281646A1 (fr) | 1976-03-05 |
| JPS5141976A (ja) | 1976-04-08 |
| DE2438256A1 (de) | 1976-02-19 |
| IT1040488B (it) | 1979-12-20 |
| US4014714A (en) | 1977-03-29 |
| GB1504636A (en) | 1978-03-22 |