DE2207264A1 - Halbleiterschaltung mit drei Anschlußebenen und Verfahren zu ihrer Herstellung. - Google Patents

Halbleiterschaltung mit drei Anschlußebenen und Verfahren zu ihrer Herstellung.

Info

Publication number
DE2207264A1
DE2207264A1 DE19722207264 DE2207264A DE2207264A1 DE 2207264 A1 DE2207264 A1 DE 2207264A1 DE 19722207264 DE19722207264 DE 19722207264 DE 2207264 A DE2207264 A DE 2207264A DE 2207264 A1 DE2207264 A1 DE 2207264A1
Authority
DE
Germany
Prior art keywords
silicon
doped
insulating layer
selectively
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
DE19722207264
Other languages
German (de)
English (en)
Inventor
James Alan; Wakefield jun. Robert Henry; Houston Tex.; Guidry jun. Mark Romain Rancho Bernardo Calif.; Cunningham (V.StA.). HOIj 29-66
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Texas Instruments Inc
Original Assignee
Texas Instruments Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Texas Instruments Inc filed Critical Texas Instruments Inc
Publication of DE2207264A1 publication Critical patent/DE2207264A1/de
Pending legal-status Critical Current

Links

Classifications

    • H10W20/20—
    • H10P95/00—
    • H10W10/011—
    • H10W10/0125—
    • H10W10/10—
    • H10W10/13—
    • H10W20/031—
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/117—Oxidation, selective
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/122—Polycrystalline
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/151—Simultaneous diffusion
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/981—Utilizing varying dielectric thickness

Landscapes

  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
DE19722207264 1971-02-16 1972-02-16 Halbleiterschaltung mit drei Anschlußebenen und Verfahren zu ihrer Herstellung. Pending DE2207264A1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US115428A US3921282A (en) 1971-02-16 1971-02-16 Insulated gate field effect transistor circuits and their method of fabrication

Publications (1)

Publication Number Publication Date
DE2207264A1 true DE2207264A1 (de) 1972-08-31

Family

ID=22361342

Family Applications (1)

Application Number Title Priority Date Filing Date
DE19722207264 Pending DE2207264A1 (de) 1971-02-16 1972-02-16 Halbleiterschaltung mit drei Anschlußebenen und Verfahren zu ihrer Herstellung.

Country Status (4)

Country Link
US (1) US3921282A (enExample)
DE (1) DE2207264A1 (enExample)
FR (1) FR2125462B1 (enExample)
NL (1) NL7202027A (enExample)

Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS598065B2 (ja) * 1976-01-30 1984-02-22 松下電子工業株式会社 Ｍｏｓ集積回路の製造方法
DE2760086C2 (enExample) * 1976-07-26 1988-02-18 Hitachi, Ltd., Tokio/Tokyo, Jp
US4151020A (en) * 1977-01-26 1979-04-24 Texas Instruments Incorporated High density N-channel silicon gate read only memory
US4102733A (en) * 1977-04-29 1978-07-25 International Business Machines Corporation Two and three mask process for IGFET fabrication
IT1097967B (it) * 1977-07-18 1985-08-31 Mostek Corp Procedimnto e struttura per l'incrocio di segnali di informazione in un dispositivo a circuito integrato
US4221044A (en) * 1978-06-06 1980-09-09 Rockwell International Corporation Self-alignment of gate contacts at local or remote sites
US4192059A (en) * 1978-06-06 1980-03-11 Rockwell International Corporation Process for and structure of high density VLSI circuits, having inherently self-aligned gates and contacts for FET devices and conducting lines
US4280271A (en) * 1979-10-11 1981-07-28 Texas Instruments Incorporated Three level interconnect process for manufacture of integrated circuit devices
JPS60116167A (ja) * 1983-11-29 1985-06-22 Toshiba Corp 半導体記憶装置及びその製造方法
JPH0644593B2 (ja) * 1984-11-09 1994-06-08 株式会社東芝 半導体集積回路装置
US4966864A (en) * 1989-03-27 1990-10-30 Motorola, Inc. Contact structure and method
US5298792A (en) * 1992-02-03 1994-03-29 Micron Technology, Inc. Integrated circuit device with bi-level contact landing pads
US5391510A (en) * 1992-02-28 1995-02-21 International Business Machines Corporation Formation of self-aligned metal gate FETs using a benignant removable gate material during high temperature steps
KR100191347B1 (ko) * 1996-08-09 1999-06-15 윤종용 반도체 공정의 주사전자현미경 관리용 미세선폭 관리시료
US6362527B1 (en) * 1996-11-21 2002-03-26 Advanced Micro Devices, Inc. Borderless vias on bottom metal
KR100446300B1 (ko) * 2002-05-30 2004-08-30 삼성전자주식회사 반도체 소자의 금속 배선 형성 방법
US20080070405A1 (en) * 2002-05-30 2008-03-20 Park Jae-Hwa Methods of forming metal wiring layers for semiconductor devices

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1001908A (en) * 1962-08-31 1965-08-18 Texas Instruments Inc Semiconductor devices
US3436611A (en) * 1965-01-25 1969-04-01 Texas Instruments Inc Insulation structure for crossover leads in integrated circuitry
DE1614928A1 (de) * 1966-07-19 1970-12-23 Solitron Devices Verfahren zur Kontaktierung von Halbleiter-Bauelementen
US3676921A (en) * 1967-06-08 1972-07-18 Philips Corp Semiconductor device comprising an insulated gate field effect transistor and method of manufacturing the same
US3535775A (en) * 1967-12-18 1970-10-27 Gen Electric Formation of small semiconductor structures
US3519901A (en) * 1968-01-29 1970-07-07 Texas Instruments Inc Bi-layer insulation structure including polycrystalline semiconductor material for integrated circuit isolation
US3576478A (en) * 1969-07-22 1971-04-27 Philco Ford Corp Igfet comprising n-type silicon substrate, silicon oxide gate insulator and p-type polycrystalline silicon gate electrode

Also Published As

Publication number Publication date
US3921282A (en) 1975-11-25
NL7202027A (enExample) 1972-08-18
FR2125462A1 (enExample) 1972-09-29
FR2125462B1 (enExample) 1977-12-23

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Legal Events

Date Code Title Description
OD Request for examination
OHW Rejection