DE2133976C3 - Monolithisch integrierte Halbleiteranordnung - Google Patents

Monolithisch integrierte Halbleiteranordnung

Info

Publication number
DE2133976C3
DE2133976C3 DE2133976A DE2133976A DE2133976C3 DE 2133976 C3 DE2133976 C3 DE 2133976C3 DE 2133976 A DE2133976 A DE 2133976A DE 2133976 A DE2133976 A DE 2133976A DE 2133976 C3 DE2133976 C3 DE 2133976C3
Authority
DE
Germany
Prior art keywords
zone
layer
semiconductor
epitaxial
insulating
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
DE2133976A
Other languages
German (de)
English (en)
Other versions
DE2133976A1 (de
DE2133976B2 (de
Inventor
Else Eindhoven Kooi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Koninklijke Philips NV
Original Assignee
Philips Gloeilampenfabrieken NV
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Philips Gloeilampenfabrieken NV filed Critical Philips Gloeilampenfabrieken NV
Publication of DE2133976A1 publication Critical patent/DE2133976A1/de
Publication of DE2133976B2 publication Critical patent/DE2133976B2/de
Application granted granted Critical
Publication of DE2133976C3 publication Critical patent/DE2133976C3/de
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/40—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00 with at least one component covered by groups H10D10/00 or H10D18/00, e.g. integration of IGFETs with BJTs
    • H10D84/401—Combinations of FETs or IGBTs with BJTs
    • H10D84/403—Combinations of FETs or IGBTs with BJTs and with one or more of diodes, resistors or capacitors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
    • H10D62/112—Constructional design considerations for preventing surface leakage or controlling electric field concentration for preventing surface leakage due to surface inversion layers, e.g. by using channel stoppers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/60—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D10/00 or H10D18/00, e.g. integration of BJTs
    • H10D84/611—Combinations of BJTs and one or more of diodes, resistors or capacitors
    • H10D84/613—Combinations of vertical BJTs and one or more of diodes, resistors or capacitors
    • H10D84/615—Combinations of vertical BJTs and one or more of resistors or capacitors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/61—Formation of materials, e.g. in the shape of layers or pillars of insulating materials using masks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H10W10/011—Manufacture or treatment of isolation regions comprising dielectric materials
    • H10W10/012—Manufacture or treatment of isolation regions comprising dielectric materials using local oxidation of silicon [LOCOS]
    • H10W10/0121—Manufacture or treatment of isolation regions comprising dielectric materials using local oxidation of silicon [LOCOS] in regions recessed from the surface, e.g. in trenches or grooves
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H10W10/011—Manufacture or treatment of isolation regions comprising dielectric materials
    • H10W10/012—Manufacture or treatment of isolation regions comprising dielectric materials using local oxidation of silicon [LOCOS]
    • H10W10/0125—Manufacture or treatment of isolation regions comprising dielectric materials using local oxidation of silicon [LOCOS] comprising introducing electrical impurities in local oxidation regions, e.g. to alter LOCOS oxide growth characteristics
    • H10W10/0126—Manufacture or treatment of isolation regions comprising dielectric materials using local oxidation of silicon [LOCOS] comprising introducing electrical impurities in local oxidation regions, e.g. to alter LOCOS oxide growth characteristics introducing electrical active impurities in local oxidation regions to create channel stoppers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/13—Isolation regions comprising dielectric materials formed using local oxidation of silicon [LOCOS], e.g. sealed interface localised oxidation [SILO] or side-wall mask isolation [SWAMI]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W15/00—Highly-doped buried regions of integrated devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W15/00—Highly-doped buried regions of integrated devices
    • H10W15/01—Manufacture or treatment

Landscapes

  • Element Separation (AREA)
  • Bipolar Transistors (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
DE2133976A 1970-07-10 1971-07-08 Monolithisch integrierte Halbleiteranordnung Expired DE2133976C3 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
NLAANVRAGE7010204,A NL170902C (nl) 1970-07-10 1970-07-10 Halfgeleiderinrichting, in het bijzonder monolithische geintegreerde halfgeleiderschakeling.

Publications (3)

Publication Number Publication Date
DE2133976A1 DE2133976A1 (de) 1972-01-13
DE2133976B2 DE2133976B2 (de) 1979-07-12
DE2133976C3 true DE2133976C3 (de) 1981-07-23

Family

ID=19810544

Family Applications (1)

Application Number Title Priority Date Filing Date
DE2133976A Expired DE2133976C3 (de) 1970-07-10 1971-07-08 Monolithisch integrierte Halbleiteranordnung

Country Status (11)

Country Link
US (1) US4903109A (enExample)
JP (1) JPS4945629B1 (enExample)
BE (1) BE769729A (enExample)
BR (1) BR7104395D0 (enExample)
CH (1) CH535496A (enExample)
DE (1) DE2133976C3 (enExample)
ES (1) ES393035A1 (enExample)
FR (1) FR2098319B1 (enExample)
GB (1) GB1364676A (enExample)
HK (2) HK59376A (enExample)
NL (1) NL170902C (enExample)

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3648125A (en) * 1971-02-02 1972-03-07 Fairchild Camera Instr Co Method of fabricating integrated circuits with oxidized isolation and the resulting structure
IT979178B (it) * 1972-05-11 1974-09-30 Ibm Resistore per dispositivi a circuito integrato
DE2235865A1 (de) * 1972-07-21 1974-01-31 Licentia Gmbh Halbleiteranordnung aus einer vielzahl von in einem gemeinsamen halbleiterkoerper untergebrachten halbleiterbauelementen
JPS598065B2 (ja) * 1976-01-30 1984-02-22 松下電子工業株式会社 Ｍｏｓ集積回路の製造方法
DE2708639A1 (de) * 1977-02-28 1978-08-31 Siemens Ag Transistoranordnung auf einem halbleiterplaettchen
FR2480036A1 (fr) * 1980-04-04 1981-10-09 Thomson Csf Structure de dispositif a semi-conducteur a anneau de garde et a fonctionnement unipolaire
JPS5931052A (ja) * 1982-08-13 1984-02-18 Hitachi Ltd 半導体集積回路装置の製造方法
US5290396A (en) * 1991-06-06 1994-03-01 Lsi Logic Corporation Trench planarization techniques
US5413966A (en) * 1990-12-20 1995-05-09 Lsi Logic Corporation Shallow trench etch
US5248625A (en) * 1991-06-06 1993-09-28 Lsi Logic Corporation Techniques for forming isolation structures
US5225358A (en) * 1991-06-06 1993-07-06 Lsi Logic Corporation Method of forming late isolation with polishing
US5252503A (en) * 1991-06-06 1993-10-12 Lsi Logic Corporation Techniques for forming isolation structures
JP3979661B2 (ja) * 1994-04-15 2007-09-19 コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ 半導体素子と電気的に接触する導体パターンを設けた支持バーによる装置の製造方法
US5783470A (en) * 1995-12-14 1998-07-21 Lsi Logic Corporation Method of making CMOS dynamic random-access memory structures and the like
KR100456691B1 (ko) * 2002-03-05 2004-11-10 삼성전자주식회사 이중격리구조를 갖는 반도체 소자 및 그 제조방법

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1077851A (en) * 1962-05-28 1967-08-02 Ultra Electronics Ltd Transistors
US3254277A (en) * 1963-02-27 1966-05-31 United Aircraft Corp Integrated circuit with component defining groove
US3386865A (en) * 1965-05-10 1968-06-04 Ibm Process of making planar semiconductor devices isolated by encapsulating oxide filled channels
US3442011A (en) * 1965-06-30 1969-05-06 Texas Instruments Inc Method for isolating individual devices in an integrated circuit monolithic bar
US3615929A (en) * 1965-07-08 1971-10-26 Texas Instruments Inc Method of forming epitaxial region of predetermined thickness and article of manufacture
NL153374B (nl) * 1966-10-05 1977-05-16 Philips Nv Werkwijze ter vervaardiging van een halfgeleiderinrichting voorzien van een oxydelaag en halfgeleiderinrichting vervaardigd volgens de werkwijze.
US3481801A (en) * 1966-10-10 1969-12-02 Frances Hugle Isolation technique for integrated circuits
US3534234A (en) * 1966-12-15 1970-10-13 Texas Instruments Inc Modified planar process for making semiconductor devices having ultrafine mesa type geometry
US3653988A (en) * 1968-02-05 1972-04-04 Bell Telephone Labor Inc Method of forming monolithic semiconductor integrated circuit devices
US3648125A (en) * 1971-02-02 1972-03-07 Fairchild Camera Instr Co Method of fabricating integrated circuits with oxidized isolation and the resulting structure

Also Published As

Publication number Publication date
HK59476A (en) 1976-10-01
DE2133976A1 (de) 1972-01-13
BE769729A (fr) 1972-01-10
GB1364676A (en) 1974-08-29
US4903109A (en) 1990-02-20
CH535496A (de) 1973-03-31
NL7010204A (enExample) 1972-01-12
DE2133976B2 (de) 1979-07-12
ES393035A1 (es) 1973-08-16
BR7104395D0 (pt) 1973-04-05
NL170902C (nl) 1983-01-03
FR2098319B1 (enExample) 1976-05-28
NL170902B (nl) 1982-08-02
FR2098319A1 (enExample) 1972-03-10
HK59376A (en) 1976-10-01
JPS4945629B1 (enExample) 1974-12-05

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Legal Events

Date Code Title Description
C3 Grant after two publication steps (3rd publication)