DE2059506C2 - Halbleiterbauelement und Verfahren zu seiner Herstellung - Google Patents

Halbleiterbauelement und Verfahren zu seiner Herstellung

Info

Publication number
DE2059506C2
DE2059506C2 DE2059506A DE2059506A DE2059506C2 DE 2059506 C2 DE2059506 C2 DE 2059506C2 DE 2059506 A DE2059506 A DE 2059506A DE 2059506 A DE2059506 A DE 2059506A DE 2059506 C2 DE2059506 C2 DE 2059506C2
Authority
DE
Germany
Prior art keywords
polycrystalline
semiconductor
area
epitaxial layer
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
DE2059506A
Other languages
German (de)
English (en)
Other versions
DE2059506A1 (de
Inventor
Joseph Juifu Shelburne Vt. Chang
Madhukar Bhavanidas Beacon N.Y. Vora
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of DE2059506A1 publication Critical patent/DE2059506A1/de
Application granted granted Critical
Publication of DE2059506C2 publication Critical patent/DE2059506C2/de
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P95/00—Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D99/00—Subject matter not provided for in other groups of this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/021—Manufacture or treatment of interconnections within wafers or substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/20—Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/085—Isolated-integrated
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/115—Orientation
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/122—Polycrystalline
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/145—Shaped junctions

Landscapes

  • Bipolar Transistors (AREA)
  • Element Separation (AREA)
DE2059506A 1970-01-28 1970-12-03 Halbleiterbauelement und Verfahren zu seiner Herstellung Expired DE2059506C2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US649370A 1970-01-28 1970-01-28

Publications (2)

Publication Number Publication Date
DE2059506A1 DE2059506A1 (de) 1971-08-05
DE2059506C2 true DE2059506C2 (de) 1983-02-24

Family

ID=21721155

Family Applications (1)

Application Number Title Priority Date Filing Date
DE2059506A Expired DE2059506C2 (de) 1970-01-28 1970-12-03 Halbleiterbauelement und Verfahren zu seiner Herstellung

Country Status (6)

Country Link
US (1) US3621346A (OSRAM)
JP (1) JPS4936790B1 (OSRAM)
CA (1) CA925223A (OSRAM)
DE (1) DE2059506C2 (OSRAM)
FR (1) FR2077371B1 (OSRAM)
GB (1) GB1325082A (OSRAM)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
NL166156C (nl) * 1971-05-22 1981-06-15 Philips Nv Halfgeleiderinrichting bevattende ten minste een op een halfgeleidersubstraatlichaam aangebrachte halfge- leiderlaag met ten minste een isolatiezone, welke een in de halfgeleiderlaag verzonken isolatielaag uit door plaatselijke thermische oxydatie van het half- geleidermateriaal van de halfgeleiderlaag gevormd isolerend materiaal bevat en een werkwijze voor het vervaardigen daarvan.
JPS4936797U (OSRAM) * 1972-06-28 1974-04-01
DE2429957B2 (de) * 1974-06-21 1980-08-28 Siemens Ag, 1000 Berlin Und 8000 Muenchen Verfahren zur Herstellung einer dotierten Zone eines bestimmten Leitungstyps in einem Halbleiterkörper
US4210470A (en) * 1979-03-05 1980-07-01 International Business Machines Corporation Epitaxial tunnels from intersecting growth planes
US4178197A (en) * 1979-03-05 1979-12-11 International Business Machines Corporation Formation of epitaxial tunnels utilizing oriented growth techniques

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3316130A (en) * 1963-05-07 1967-04-25 Gen Electric Epitaxial growth of semiconductor devices
US3475661A (en) * 1966-02-09 1969-10-28 Sony Corp Semiconductor device including polycrystalline areas among monocrystalline areas
US3433684A (en) * 1966-09-13 1969-03-18 North American Rockwell Multilayer semiconductor heteroepitaxial structure
US3681668A (en) * 1967-11-14 1972-08-01 Sony Corp Semiconductor device and a method of making the same
US3648128A (en) * 1968-05-25 1972-03-07 Sony Corp An integrated complementary transistor circuit chip with polycrystalline contact to buried collector regions

Also Published As

Publication number Publication date
FR2077371B1 (OSRAM) 1974-03-22
JPS4936790B1 (OSRAM) 1974-10-03
DE2059506A1 (de) 1971-08-05
FR2077371A1 (OSRAM) 1971-10-22
CA925223A (en) 1973-04-24
GB1325082A (en) 1973-08-01
US3621346A (en) 1971-11-16

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Legal Events

Date Code Title Description
D2 Grant after examination
8363 Opposition against the patent
8339 Ceased/non-payment of the annual fee