DE2054535B2 - Verfahren zur Herstellung von Feldeffekt-Halbleiteranordnungen in einem Halbleiterplättchen - Google Patents

Verfahren zur Herstellung von Feldeffekt-Halbleiteranordnungen in einem Halbleiterplättchen

Info

Publication number
DE2054535B2
DE2054535B2 DE2054535A DE2054535A DE2054535B2 DE 2054535 B2 DE2054535 B2 DE 2054535B2 DE 2054535 A DE2054535 A DE 2054535A DE 2054535 A DE2054535 A DE 2054535A DE 2054535 B2 DE2054535 B2 DE 2054535B2
Authority
DE
Germany
Prior art keywords
gate
mask layer
semiconductor
nitride
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
DE2054535A
Other languages
German (de)
English (en)
Other versions
DE2054535A1 (de
Inventor
Ronald Eugene Placentia Calif. Harris (V.St.A.)
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Boeing North American Inc
Original Assignee
Rockwell International Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Rockwell International Corp filed Critical Rockwell International Corp
Publication of DE2054535A1 publication Critical patent/DE2054535A1/de
Publication of DE2054535B2 publication Critical patent/DE2054535B2/de
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P95/00—Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/61—Formation of materials, e.g. in the shape of layers or pillars of insulating materials using masks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H10W10/011—Manufacture or treatment of isolation regions comprising dielectric materials
    • H10W10/012—Manufacture or treatment of isolation regions comprising dielectric materials using local oxidation of silicon [LOCOS]
    • H10W10/0121—Manufacture or treatment of isolation regions comprising dielectric materials using local oxidation of silicon [LOCOS] in regions recessed from the surface, e.g. in trenches or grooves
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/13—Isolation regions comprising dielectric materials formed using local oxidation of silicon [LOCOS], e.g. sealed interface localised oxidation [SILO] or side-wall mask isolation [SWAMI]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/40—Encapsulations, e.g. protective coatings characterised by their materials
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/043—Dual dielectric
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/051—Etching
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/053—Field effect transistors fets
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/085—Isolated-integrated
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/114—Nitrides of silicon
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/117—Oxidation, selective
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/15—Silicon on sapphire SOS

Landscapes

  • Element Separation (AREA)
  • Local Oxidation Of Silicon (AREA)
  • Weting (AREA)
DE2054535A 1970-02-26 1970-11-05 Verfahren zur Herstellung von Feldeffekt-Halbleiteranordnungen in einem Halbleiterplättchen Withdrawn DE2054535B2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US1431970A 1970-02-26 1970-02-26

Publications (2)

Publication Number Publication Date
DE2054535A1 DE2054535A1 (de) 1971-09-09
DE2054535B2 true DE2054535B2 (de) 1979-04-19

Family

ID=21764759

Family Applications (1)

Application Number Title Priority Date Filing Date
DE2054535A Withdrawn DE2054535B2 (de) 1970-02-26 1970-11-05 Verfahren zur Herstellung von Feldeffekt-Halbleiteranordnungen in einem Halbleiterplättchen

Country Status (6)

Country Link
US (1) US3698966A (oth)
JP (1) JPS514837B1 (oth)
DE (1) DE2054535B2 (oth)
FR (1) FR2080769B1 (oth)
GB (2) GB1345528A (oth)
NL (1) NL7015048A (oth)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3865653A (en) * 1971-10-12 1975-02-11 Karl Goser Logic circuit having a switching transistor and a load transistor, in particular for a semiconductor storage element
DE2314260A1 (de) * 1972-05-30 1973-12-13 Ibm Ladungsgekoppelte halbleiteranordnung und verfahren zu ihrer herstellung
DE2318912A1 (de) * 1972-06-30 1974-01-17 Ibm Integrierte halbleiteranordnung
US3885994A (en) * 1973-05-25 1975-05-27 Trw Inc Bipolar transistor construction method
JPS51118384A (en) * 1975-04-10 1976-10-18 Matsushita Electric Ind Co Ltd Manufacturing prouss for mos type semiconductor unit
JPS5267963A (en) * 1975-12-04 1977-06-06 Mitsubishi Electric Corp Manufacture of semiconductor unit
US4070211A (en) * 1977-04-04 1978-01-24 The United States Of America As Represented By The Secretary Of The Navy Technique for threshold control over edges of devices on silicon-on-sapphire
NL7903158A (nl) * 1979-04-23 1980-10-27 Philips Nv Werkwijze voor het vervaardigen van een veldeffekt- transistor met geisoleerde poortelektrode, en transistor vervaardigd door toepassing van een derge- lijke werkwijze.
JPS6018151B2 (ja) * 1980-11-10 1985-05-09 日本電気株式会社 絶縁ゲ−ト型電界効果トランジスタの製造方法
JPS57211267A (en) * 1981-06-22 1982-12-25 Toshiba Corp Semiconductor device and manufacture thereof

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
NL153374B (nl) * 1966-10-05 1977-05-16 Philips Nv Werkwijze ter vervaardiging van een halfgeleiderinrichting voorzien van een oxydelaag en halfgeleiderinrichting vervaardigd volgens de werkwijze.
NL152707B (nl) * 1967-06-08 1977-03-15 Philips Nv Halfgeleiderinrichting bevattende een veldeffecttransistor van het type met geisoleerde poortelektrode en werkwijze ter vervaardiging daarvan.

Also Published As

Publication number Publication date
GB1345528A (en) 1974-01-30
DE2054535A1 (de) 1971-09-09
NL7015048A (oth) 1971-08-30
US3698966A (en) 1972-10-17
GB1345527A (en) 1974-01-30
FR2080769B1 (oth) 1974-09-27
JPS514837B1 (oth) 1976-02-14
FR2080769A1 (oth) 1971-11-19

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Legal Events

Date Code Title Description
OGA New person/name/address of the applicant
8230 Patent withdrawn