DE19882933T1 - Flash-Speicher-Unterteilung für Lese-während-Schreiboperationen - Google Patents

Flash-Speicher-Unterteilung für Lese-während-Schreiboperationen

Info

Publication number
DE19882933T1
DE19882933T1 DE19882933T DE19882933T DE19882933T1 DE 19882933 T1 DE19882933 T1 DE 19882933T1 DE 19882933 T DE19882933 T DE 19882933T DE 19882933 T DE19882933 T DE 19882933T DE 19882933 T1 DE19882933 T1 DE 19882933T1
Authority
DE
Germany
Prior art keywords
read
flash memory
write operations
memory division
division
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
DE19882933T
Other languages
English (en)
Other versions
DE19882933B4 (de
Inventor
Peter K Hazen
Robert E Larsen
Ranjeet Alexis
Charles W Brown
Sanjay Talreja
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Intel Corp
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Publication of DE19882933T1 publication Critical patent/DE19882933T1/de
Application granted granted Critical
Publication of DE19882933B4 publication Critical patent/DE19882933B4/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/26—Sensing or reading circuits; Data output circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2216/00—Indexing scheme relating to G11C16/00 and subgroups, for features not directly covered by these groups
    • G11C2216/12—Reading and writing aspects of erasable programmable read-only memories
    • G11C2216/22—Nonvolatile memory in which reading can be carried out from one memory bank or array whilst a word or sector in another bank or array is being erased or programmed simultaneously
DE19882933T 1998-01-05 1998-11-24 Flash-Speicher-Unterteilung für Lese-während-Schreiboperationen Expired - Fee Related DE19882933B4 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US09/002,649 US6088264A (en) 1998-01-05 1998-01-05 Flash memory partitioning for read-while-write operation
US09/002,649 1998-01-05
PCT/US1998/025217 WO1999035650A1 (en) 1998-01-05 1998-11-24 Flash memory partitioning for read-while-write operation

Publications (2)

Publication Number Publication Date
DE19882933T1 true DE19882933T1 (de) 2001-01-18
DE19882933B4 DE19882933B4 (de) 2006-05-18

Family

ID=21701801

Family Applications (1)

Application Number Title Priority Date Filing Date
DE19882933T Expired - Fee Related DE19882933B4 (de) 1998-01-05 1998-11-24 Flash-Speicher-Unterteilung für Lese-während-Schreiboperationen

Country Status (9)

Country Link
US (1) US6088264A (de)
JP (1) JP4414087B2 (de)
KR (1) KR100388949B1 (de)
AU (1) AU1536899A (de)
DE (1) DE19882933B4 (de)
GB (1) GB2347767B (de)
HK (1) HK1027206A1 (de)
TW (1) TW455911B (de)
WO (1) WO1999035650A1 (de)

Families Citing this family (39)

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US6345000B1 (en) 1997-04-16 2002-02-05 Sandisk Corporation Flash memory permitting simultaneous read/write and erase operations in a single memory array
US6591327B1 (en) * 1999-06-22 2003-07-08 Silicon Storage Technology, Inc. Flash memory with alterable erase sector size
EP1073064A1 (de) 1999-07-30 2001-01-31 STMicroelectronics S.r.l. Nichtflüchtiger Speicher mit die funktioneller Fähigkeit von Inhaltsveränderung und gleichzeitig Burst- oder Seitenmoduslesung
US6407949B1 (en) * 1999-12-17 2002-06-18 Qualcomm, Incorporated Mobile communication device having integrated embedded flash and SRAM memory
US6662263B1 (en) 2000-03-03 2003-12-09 Multi Level Memory Technology Sectorless flash memory architecture
US6240040B1 (en) * 2000-03-15 2001-05-29 Advanced Micro Devices, Inc. Multiple bank simultaneous operation for a flash memory
US6851026B1 (en) * 2000-07-28 2005-02-01 Micron Technology, Inc. Synchronous flash memory with concurrent write and read operation
FR2809223A1 (fr) * 2000-05-17 2001-11-23 Schlumberger Systems & Service Effacement d'eeprom en temps masque
US6772273B1 (en) 2000-06-29 2004-08-03 Intel Corporation Block-level read while write method and apparatus
US6748482B1 (en) 2000-09-27 2004-06-08 Intel Corporation Multiple non-contiguous block erase in flash memory
ES2260102T3 (es) * 2000-10-16 2006-11-01 Stmicroelectronics S.R.L. Dispositvo de control para vehiculo a motor.
US6931498B2 (en) * 2001-04-03 2005-08-16 Intel Corporation Status register architecture for flexible read-while-write device
US6584034B1 (en) * 2001-04-23 2003-06-24 Aplus Flash Technology Inc. Flash memory array structure suitable for multiple simultaneous operations
US7062616B2 (en) * 2001-06-12 2006-06-13 Intel Corporation Implementing a dual partition flash with suspend/resume capabilities
JP3827540B2 (ja) * 2001-06-28 2006-09-27 シャープ株式会社 不揮発性半導体記憶装置および情報機器
US6628563B1 (en) 2001-07-09 2003-09-30 Aplus Flash Technology, Inc. Flash memory array for multiple simultaneous operations
US6614685B2 (en) 2001-08-09 2003-09-02 Multi Level Memory Technology Flash memory array partitioning architectures
US6781914B2 (en) 2001-08-23 2004-08-24 Winbond Electronics Corp. Flash memory having a flexible bank partition
US7177197B2 (en) * 2001-09-17 2007-02-13 Sandisk Corporation Latched programming of memory and method
US6741502B1 (en) * 2001-09-17 2004-05-25 Sandisk Corporation Background operation for memory cells
US7562208B1 (en) * 2002-02-07 2009-07-14 Network Appliance, Inc. Method and system to quarantine system software and configuration
EP1376608A1 (de) * 2002-06-28 2004-01-02 Cp8 Programmierverfahren in einem nichtflüchtigen Speicher und System zur Realisierung eines solchen Verfahrens
JP4101583B2 (ja) * 2002-08-08 2008-06-18 富士通株式会社 消去動作時間を短縮したフラッシュメモリ
CN100433194C (zh) * 2002-12-10 2008-11-12 华邦电子股份有限公司 具有弹性排区分区的闪存及形成方法
KR101107288B1 (ko) * 2003-12-17 2012-01-20 엘지전자 주식회사 다중 분할된 플래시 메모리 장치 및 분할된 메모리에데이터를 저장하기 위한 이중 저널링 저장방법
US7388789B2 (en) * 2005-08-31 2008-06-17 Micron Technology NAND memory device and programming methods
US7292473B2 (en) * 2005-09-07 2007-11-06 Freescale Semiconductor, Inc. Method and apparatus for programming/erasing a non-volatile memory
US7652922B2 (en) 2005-09-30 2010-01-26 Mosaid Technologies Incorporated Multiple independent serial link memory
US7562180B2 (en) 2006-03-28 2009-07-14 Nokia Corporation Method and device for reduced read latency of non-volatile memory
US7573744B2 (en) * 2006-09-29 2009-08-11 Kabushiki Kaisha Toshiba Semiconductor memory device having different capacity areas
JP4996277B2 (ja) * 2007-02-09 2012-08-08 株式会社東芝 半導体記憶システム
US7613051B2 (en) * 2007-03-14 2009-11-03 Apple Inc. Interleaving charge pumps for programmable memories
KR20110005788A (ko) * 2008-02-19 2011-01-19 램버스 인코포레이티드 할당 가능 자원을 갖는 멀티-뱅크 플래시 메모리 구조
KR101438072B1 (ko) 2010-04-15 2014-09-03 라모트 앳 텔-아비브 유니버시티 리미티드 소거 없는 플래시 메모리의 다중 프로그래밍
WO2011132245A1 (ja) * 2010-04-19 2011-10-27 パナソニック株式会社 コンテンツ受信端末、エキスポート再生方法、および記録媒体
KR20120015725A (ko) 2010-08-13 2012-02-22 삼성전자주식회사 전압 제어 방법 및 이를 이용한 메모리 장치
US9496046B1 (en) 2015-08-14 2016-11-15 Integrated Silicon Solution, Inc. High speed sequential read method for flash memory
KR102425259B1 (ko) 2015-11-27 2022-07-27 에스케이하이닉스 주식회사 비휘발성 메모리 장치, 반도체 장치 및 반도체 장치의 동작 방법
JP6753746B2 (ja) 2016-09-15 2020-09-09 キオクシア株式会社 半導体記憶装置

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5245572A (en) * 1991-07-30 1993-09-14 Intel Corporation Floating gate nonvolatile memory with reading while writing capability
US5361227A (en) * 1991-12-19 1994-11-01 Kabushiki Kaisha Toshiba Non-volatile semiconductor memory device and memory system using the same
US5490107A (en) * 1991-12-27 1996-02-06 Fujitsu Limited Nonvolatile semiconductor memory
JP2865469B2 (ja) * 1992-01-24 1999-03-08 三菱電機株式会社 半導体メモリ装置
JPH05303897A (ja) * 1992-04-24 1993-11-16 Matsushita Electric Ind Co Ltd 半導体装置
JP3105092B2 (ja) * 1992-10-06 2000-10-30 株式会社東芝 半導体メモリ装置
TW235363B (de) * 1993-01-25 1994-12-01 Hitachi Seisakusyo Kk
US5483486A (en) * 1994-10-19 1996-01-09 Intel Corporation Charge pump circuit for providing multiple output voltages for flash memory
JPH08263361A (ja) * 1995-03-23 1996-10-11 Mitsubishi Electric Corp フラッシュメモリカード
DE69514502T2 (de) * 1995-05-05 2000-08-03 St Microelectronics Srl Nichtflüchtige Speicheranordnung mit Sektoren, deren Grösse und Anzahl bestimmbar sind
DE69520665T2 (de) * 1995-05-05 2001-08-30 St Microelectronics Srl Anordnung von nichtflüchtigen EEPROM,insbesondere Flash-EEPROM
JP3153730B2 (ja) * 1995-05-16 2001-04-09 株式会社東芝 不揮発性半導体記憶装置
US5815434A (en) * 1995-09-29 1998-09-29 Intel Corporation Multiple writes per a single erase for a nonvolatile memory
US5796657A (en) * 1996-03-29 1998-08-18 Aplus Integrated Circuits, Inc. Flash memory with flexible erasing size from multi-byte to multi-block
US5732030A (en) * 1996-06-25 1998-03-24 Texas Instruments Incorporated Method and system for reduced column redundancy using a dual column select
US5867430A (en) * 1996-12-20 1999-02-02 Advanced Micro Devices Inc Bank architecture for a non-volatile memory enabling simultaneous reading and writing
US5917744A (en) * 1997-12-18 1999-06-29 Siemens Aktiengesellschaft Semiconductor memory having hierarchical bit line architecture with interleaved master bitlines

Also Published As

Publication number Publication date
GB2347767A (en) 2000-09-13
JP2002501276A (ja) 2002-01-15
KR100388949B1 (ko) 2003-06-25
TW455911B (en) 2001-09-21
WO1999035650A1 (en) 1999-07-15
HK1027206A1 (en) 2001-01-05
AU1536899A (en) 1999-07-26
DE19882933B4 (de) 2006-05-18
GB2347767B (en) 2002-03-27
KR20010024835A (ko) 2001-03-26
JP4414087B2 (ja) 2010-02-10
GB0014299D0 (en) 2000-08-02
US6088264A (en) 2000-07-11

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Legal Events

Date Code Title Description
OP8 Request for examination as to paragraph 44 patent law
8364 No opposition during term of opposition
R119 Application deemed withdrawn, or ip right lapsed, due to non-payment of renewal fee