DE19638433B4 - Verfahren zur Herstellung einer Halbleitervorrichtung - Google Patents

Verfahren zur Herstellung einer Halbleitervorrichtung Download PDF

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Publication number
DE19638433B4
DE19638433B4 DE19638433A DE19638433A DE19638433B4 DE 19638433 B4 DE19638433 B4 DE 19638433B4 DE 19638433 A DE19638433 A DE 19638433A DE 19638433 A DE19638433 A DE 19638433A DE 19638433 B4 DE19638433 B4 DE 19638433B4
Authority
DE
Germany
Prior art keywords
wiring
film
insulating film
electrode
gate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE19638433A
Other languages
German (de)
English (en)
Other versions
DE19638433A1 (de
Inventor
Shunpei Yamazaki
Jun Sagamihara Koyama
Yasushi Atsugi Ogata
Satoshi Atsugi Teramoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Semiconductor Energy Laboratory Co Ltd
Original Assignee
Semiconductor Energy Laboratory Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Semiconductor Energy Laboratory Co Ltd filed Critical Semiconductor Energy Laboratory Co Ltd
Publication of DE19638433A1 publication Critical patent/DE19638433A1/de
Application granted granted Critical
Publication of DE19638433B4 publication Critical patent/DE19638433B4/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1345—Conductors connecting electrodes to cell terminals
    • G02F1/13454—Drivers integrated on the active matrix substrate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/441—Interconnections, e.g. scanning lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • H10W20/01—
    • H10W20/031—

Landscapes

  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Mathematical Physics (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • General Physics & Mathematics (AREA)
  • Optics & Photonics (AREA)
  • Thin Film Transistor (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
DE19638433A 1995-09-21 1996-09-19 Verfahren zur Herstellung einer Halbleitervorrichtung Expired - Fee Related DE19638433B4 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP26794295 1995-09-21
JPP7-267942 1995-09-21

Publications (2)

Publication Number Publication Date
DE19638433A1 DE19638433A1 (de) 1997-03-27
DE19638433B4 true DE19638433B4 (de) 2007-01-25

Family

ID=17451750

Family Applications (1)

Application Number Title Priority Date Filing Date
DE19638433A Expired - Fee Related DE19638433B4 (de) 1995-09-21 1996-09-19 Verfahren zur Herstellung einer Halbleitervorrichtung

Country Status (4)

Country Link
US (1) US6013542A (cg-RX-API-DMAC10.html)
KR (1) KR100297064B1 (cg-RX-API-DMAC10.html)
DE (1) DE19638433B4 (cg-RX-API-DMAC10.html)
TW (1) TW318261B (cg-RX-API-DMAC10.html)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6893980B1 (en) * 1996-12-03 2005-05-17 Kabushiki Kaisha Toshiba Semiconductor device and manufacturing method therefor
KR100276225B1 (ko) * 1998-06-01 2000-12-15 구본준 액정표시장치의 패드 단락 방지구조 및 그 방법
US6140162A (en) * 1998-06-19 2000-10-31 Lg Electronics Inc. Reduction of masking and doping steps in a method of fabricating a liquid crystal display
US6506635B1 (en) 1999-02-12 2003-01-14 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device, and method of forming the same
JP3954532B2 (ja) * 2003-06-13 2007-08-08 沖電気工業株式会社 Ｓｏｉ半導体装置の製造方法及びｓｏｉ半導体装置
TWI366701B (en) * 2004-01-26 2012-06-21 Semiconductor Energy Lab Method of manufacturing display and television
US7371625B2 (en) * 2004-02-13 2008-05-13 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and manufacturing method thereof, liquid crystal television system, and EL television system
US7183147B2 (en) 2004-03-25 2007-02-27 Semiconductor Energy Laboratory Co., Ltd. Light emitting device, method for manufacturing thereof and electronic appliance
KR101845480B1 (ko) 2010-06-25 2018-04-04 가부시키가이샤 한도오따이 에네루기 켄큐쇼 반도체 장치의 제작 방법
TWI611582B (zh) 2013-04-10 2018-01-11 半導體能源研究所股份有限公司 半導體裝置及其製造方法

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0524818A1 (en) * 1991-07-23 1993-01-27 Nec Corporation Multi-layer wiring structure in a semiconductor device and method of manufacturing the same
US5359206A (en) * 1989-08-14 1994-10-25 Hitachi, Ltd. Thin film transistor substrate, liquid crystal display panel and liquid crystal display equipment

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
IT1213261B (it) * 1984-12-20 1989-12-14 Sgs Thomson Microelectronics Dispositivo a semiconduttore con metallizzazione a piu' spessori eprocedimento per la sua fabbricazione.
US4740485A (en) * 1986-07-22 1988-04-26 Monolithic Memories, Inc. Method for forming a fuse
JPH01248536A (ja) * 1988-03-30 1989-10-04 Toshiba Corp 半導体装置の製造方法
JPH02285658A (ja) * 1989-04-26 1990-11-22 Nec Corp 半導体装置の製造方法
JPH04302166A (ja) * 1991-03-29 1992-10-26 Matsushita Electron Corp 半導体装置の製造方法
JP3019453B2 (ja) * 1991-03-30 2000-03-13 日本電気株式会社 半導体装置の製造方法
US5219793A (en) * 1991-06-03 1993-06-15 Motorola Inc. Method for forming pitch independent contacts and a semiconductor device having the same
US5422293A (en) * 1991-12-24 1995-06-06 Casio Computer Co., Ltd. Method for manufacturing a TFT panel
US5258328A (en) * 1992-03-16 1993-11-02 Kabushiki Kaisha Toshiba Method of forming multilayered wiring structure of semiconductor device
KR950008931B1 (ko) * 1992-07-22 1995-08-09 삼성전자주식회사 표시패널의 제조방법
JPH07221174A (ja) * 1993-12-10 1995-08-18 Canon Inc 半導体装置及びその製造方法
US5470790A (en) * 1994-10-17 1995-11-28 Intel Corporation Via hole profile and method of fabrication

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5359206A (en) * 1989-08-14 1994-10-25 Hitachi, Ltd. Thin film transistor substrate, liquid crystal display panel and liquid crystal display equipment
EP0524818A1 (en) * 1991-07-23 1993-01-27 Nec Corporation Multi-layer wiring structure in a semiconductor device and method of manufacturing the same

Also Published As

Publication number Publication date
US6013542A (en) 2000-01-11
TW318261B (cg-RX-API-DMAC10.html) 1997-10-21
KR100297064B1 (ko) 2001-10-24
DE19638433A1 (de) 1997-03-27

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Legal Events

Date Code Title Description
8110 Request for examination paragraph 44
8364 No opposition during term of opposition
R119 Application deemed withdrawn, or ip right lapsed, due to non-payment of renewal fee
R119 Application deemed withdrawn, or ip right lapsed, due to non-payment of renewal fee

Effective date: 20150401