DE1764951B1 - Mehrschichtige metallisierung fuer halbleiteranschluesse - Google Patents

Mehrschichtige metallisierung fuer halbleiteranschluesse

Info

Publication number
DE1764951B1
DE1764951B1 DE19681764951 DE1764951A DE1764951B1 DE 1764951 B1 DE1764951 B1 DE 1764951B1 DE 19681764951 DE19681764951 DE 19681764951 DE 1764951 A DE1764951 A DE 1764951A DE 1764951 B1 DE1764951 B1 DE 1764951B1
Authority
DE
Germany
Prior art keywords
layer
semiconductor
copper
glass
connections
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
DE19681764951
Other languages
German (de)
English (en)
Inventor
Mutter Walter Edward
Paul Totta
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of DE1764951B1 publication Critical patent/DE1764951B1/de
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P95/00—Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/251—Materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/921—Structures or relative sizes of bond pads
    • H10W72/923—Bond pads having multiple stacked layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/951—Materials of bond pads
    • H10W72/952—Materials of bond pads comprising metals or metalloids, e.g. PbSn, Ag or Cu

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Parts Printed On Printed Circuit Boards (AREA)
  • Manufacturing Of Printed Wiring (AREA)
DE19681764951 1967-09-15 1968-09-11 Mehrschichtige metallisierung fuer halbleiteranschluesse Pending DE1764951B1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US66811567A 1967-09-15 1967-09-15

Publications (1)

Publication Number Publication Date
DE1764951B1 true DE1764951B1 (de) 1972-03-16

Family

ID=24681078

Family Applications (1)

Application Number Title Priority Date Filing Date
DE19681764951 Pending DE1764951B1 (de) 1967-09-15 1968-09-11 Mehrschichtige metallisierung fuer halbleiteranschluesse

Country Status (7)

Country Link
US (1) US3461357A (https=)
CH (1) CH481487A (https=)
DE (1) DE1764951B1 (https=)
FR (1) FR1578564A (https=)
GB (1) GB1233466A (https=)
NL (1) NL6812711A (https=)
SE (1) SE351748B (https=)

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US3879840A (en) * 1969-01-15 1975-04-29 Ibm Copper doped aluminum conductive stripes and method therefor
US3838442A (en) * 1970-04-15 1974-09-24 Ibm Semiconductor structure having metallization inlaid in insulating layers and method for making same
US3675092A (en) * 1970-07-13 1972-07-04 Signetics Corp Surface controlled avalanche semiconductor device
US3668484A (en) * 1970-10-28 1972-06-06 Rca Corp Semiconductor device with multi-level metalization and method of making the same
US4005472A (en) * 1975-05-19 1977-01-25 National Semiconductor Corporation Method for gold plating of metallic layers on semiconductive devices
JPS5851425B2 (ja) * 1975-08-22 1983-11-16 株式会社日立製作所 ハンドウタイソウチ
US4035827A (en) * 1976-04-29 1977-07-12 Rca Corporation Thermally ballasted semiconductor device
FR2350697A1 (fr) * 1976-05-06 1977-12-02 Cii Structure perfectionnee de circuits multicouches
EP0042943A1 (en) * 1980-07-02 1982-01-06 International Business Machines Corporation Multilayer integrated circuit substrate structure and process for making such structures
US4307179A (en) * 1980-07-03 1981-12-22 International Business Machines Corporation Planar metal interconnection system and process
US4434434A (en) 1981-03-30 1984-02-28 International Business Machines Corporation Solder mound formation on substrates
JPS6136946A (ja) * 1984-07-30 1986-02-21 Nec Corp 半導体装置
US5170931A (en) * 1987-03-11 1992-12-15 International Business Machines Corporation Method and apparatus for mounting a flexible film semiconductor chip carrier on a circuitized substrate
US4788767A (en) * 1987-03-11 1988-12-06 International Business Machines Corporation Method for mounting a flexible film semiconductor chip carrier on a circuitized substrate
US5159535A (en) * 1987-03-11 1992-10-27 International Business Machines Corporation Method and apparatus for mounting a flexible film semiconductor chip carrier on a circuitized substrate
JPH0744188B2 (ja) * 1989-04-28 1995-05-15 株式会社東海理化電機製作所 バイポーラトランジスタ
US5281684A (en) * 1992-04-30 1994-01-25 Motorola, Inc. Solder bumping of integrated circuit die
US5767580A (en) * 1993-04-30 1998-06-16 Lsi Logic Corporation Systems having shaped, self-aligning micro-bump structures
US5477086A (en) * 1993-04-30 1995-12-19 Lsi Logic Corporation Shaped, self-aligning micro-bump structures
US5468984A (en) * 1994-11-02 1995-11-21 Texas Instruments Incorporated ESD protection structure using LDMOS diodes with thick copper interconnect
US6388203B1 (en) 1995-04-04 2002-05-14 Unitive International Limited Controlled-shaped solder reservoirs for increasing the volume of solder bumps, and structures formed thereby
EP0819318B1 (en) 1995-04-05 2003-05-14 Unitive International Limited A solder bump structure for a microelectronic substrate
US5789271A (en) * 1996-03-18 1998-08-04 Micron Technology, Inc. Method for fabricating microbump interconnect for bare semiconductor dice
US6078100A (en) * 1999-01-13 2000-06-20 Micron Technology, Inc. Utilization of die repattern layers for die internal connections
EP1031873A3 (en) 1999-02-23 2005-02-23 Sel Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and fabrication method thereof
US6710446B2 (en) * 1999-12-30 2004-03-23 Renesas Technology Corporation Semiconductor device comprising stress relaxation layers and method for manufacturing the same
JP3568869B2 (ja) * 2000-02-28 2004-09-22 シャープ株式会社 半導体集積回路装置及びその製造方法
DE60108413T2 (de) 2000-11-10 2005-06-02 Unitive Electronics, Inc. Verfahren zum positionieren von komponenten mit hilfe flüssiger antriebsmittel und strukturen hierfür
JP3526548B2 (ja) * 2000-11-29 2004-05-17 松下電器産業株式会社 半導体装置及びその製造方法
US6863209B2 (en) 2000-12-15 2005-03-08 Unitivie International Limited Low temperature methods of bonding components
US6577002B1 (en) * 2001-11-29 2003-06-10 Sun Microsystems, Inc. 180 degree bump placement layout for an integrated circuit power grid
AU2003256360A1 (en) * 2002-06-25 2004-01-06 Unitive International Limited Methods of forming electronic structures including conductive shunt layers and related structures
US7531898B2 (en) 2002-06-25 2009-05-12 Unitive International Limited Non-Circular via holes for bumping pads and related structures
US7547623B2 (en) 2002-06-25 2009-06-16 Unitive International Limited Methods of forming lead free solder bumps
TWI225899B (en) 2003-02-18 2005-01-01 Unitive Semiconductor Taiwan C Etching solution and method for manufacturing conductive bump using the etching solution to selectively remove barrier layer
US7049216B2 (en) * 2003-10-14 2006-05-23 Unitive International Limited Methods of providing solder structures for out plane connections
TW200603698A (en) 2004-04-13 2006-01-16 Unitive International Ltd Methods of forming solder bumps on exposed metal pads and related structures
US20060205170A1 (en) * 2005-03-09 2006-09-14 Rinne Glenn A Methods of forming self-healing metal-insulator-metal (MIM) structures and related devices
US7932615B2 (en) 2006-02-08 2011-04-26 Amkor Technology, Inc. Electronic devices including solder bumps on compliant dielectric layers
US7674701B2 (en) 2006-02-08 2010-03-09 Amkor Technology, Inc. Methods of forming metal layers using multi-layer lift-off patterns
EP1837910A1 (fr) * 2006-03-21 2007-09-26 Stmicroelectronics Sa Puce de circuits integrés à plots externes decalés et procédé de fabrication d'une telle puce.
JP2008258499A (ja) * 2007-04-06 2008-10-23 Sanyo Electric Co Ltd 電極構造及び半導体装置
US8304909B2 (en) * 2007-12-19 2012-11-06 Intel Corporation IC solder reflow method and materials
US7928534B2 (en) * 2008-10-09 2011-04-19 Taiwan Semiconductor Manufacturing Company, Ltd. Bond pad connection to redistribution lines having tapered profiles
US7956442B2 (en) * 2008-10-09 2011-06-07 Taiwan Semiconductor Manufacturing Company, Ltd. Backside connection to TSVs having redistribution lines
US8736050B2 (en) 2009-09-03 2014-05-27 Taiwan Semiconductor Manufacturing Company, Ltd. Front side copper post joint structure for temporary bond in TSV application
US8759949B2 (en) * 2009-04-30 2014-06-24 Taiwan Semiconductor Manufacturing Company, Ltd. Wafer backside structures having copper pillars
US8158489B2 (en) 2009-06-26 2012-04-17 Taiwan Semiconductor Manufacturing Company, Ltd. Formation of TSV backside interconnects by modifying carrier wafers
US8174124B2 (en) 2010-04-08 2012-05-08 Taiwan Semiconductor Manufacturing Co., Ltd. Dummy pattern in wafer backside routing
US8492892B2 (en) * 2010-12-08 2013-07-23 International Business Machines Corporation Solder bump connections
US9698079B2 (en) * 2014-01-03 2017-07-04 Taiwan Semiconductor Manufacturing Company, Ltd. Barrier structures between external electrical connectors
US10276402B2 (en) * 2016-03-21 2019-04-30 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor package and manufacturing process thereof

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3266127A (en) * 1964-01-27 1966-08-16 Ibm Method of forming contacts on semiconductors
US3290753A (en) * 1963-08-19 1966-12-13 Bell Telephone Labor Inc Method of making semiconductor integrated circuit elements
US3409809A (en) * 1966-04-06 1968-11-05 Irc Inc Semiconductor or write tri-layered metal contact

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3241931A (en) * 1963-03-01 1966-03-22 Rca Corp Semiconductor devices
US3290565A (en) * 1963-10-24 1966-12-06 Philco Corp Glass enclosed, passivated semiconductor with contact means of alternate layers of chromium, silver and chromium
US3290570A (en) * 1964-04-28 1966-12-06 Texas Instruments Inc Multilevel expanded metallic contacts for semiconductor devices

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3290753A (en) * 1963-08-19 1966-12-13 Bell Telephone Labor Inc Method of making semiconductor integrated circuit elements
US3266127A (en) * 1964-01-27 1966-08-16 Ibm Method of forming contacts on semiconductors
US3409809A (en) * 1966-04-06 1968-11-05 Irc Inc Semiconductor or write tri-layered metal contact

Also Published As

Publication number Publication date
GB1233466A (https=) 1971-05-26
NL6812711A (https=) 1969-03-18
SE351748B (https=) 1972-12-04
US3461357A (en) 1969-08-12
CH481487A (de) 1969-11-15
FR1578564A (https=) 1969-08-14

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