CH481487A - Mehrschichtiges, metallisiertes, auf der Oberfläche eines planaren Halbleiterkörpers angeordnetes Verbindungs- und Anschlussnetz - Google Patents

Mehrschichtiges, metallisiertes, auf der Oberfläche eines planaren Halbleiterkörpers angeordnetes Verbindungs- und Anschlussnetz

Info

Publication number
CH481487A
CH481487A CH1247268A CH1247268A CH481487A CH 481487 A CH481487 A CH 481487A CH 1247268 A CH1247268 A CH 1247268A CH 1247268 A CH1247268 A CH 1247268A CH 481487 A CH481487 A CH 481487A
Authority
CH
Switzerland
Prior art keywords
connection
layer
semiconductor body
planar semiconductor
metallized
Prior art date
Application number
CH1247268A
Other languages
English (en)
Inventor
Edward Mutter Walter
Anthony Totta Paul
Original Assignee
Ibm
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ibm filed Critical Ibm
Publication of CH481487A publication Critical patent/CH481487A/de

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
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    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
    • H01L23/485—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
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    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
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    • H01L2924/14—Integrated circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Parts Printed On Printed Circuit Boards (AREA)
  • Manufacturing Of Printed Wiring (AREA)
CH1247268A 1967-09-15 1968-08-19 Mehrschichtiges, metallisiertes, auf der Oberfläche eines planaren Halbleiterkörpers angeordnetes Verbindungs- und Anschlussnetz CH481487A (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US66811567A 1967-09-15 1967-09-15

Publications (1)

Publication Number Publication Date
CH481487A true CH481487A (de) 1969-11-15

Family

ID=24681078

Family Applications (1)

Application Number Title Priority Date Filing Date
CH1247268A CH481487A (de) 1967-09-15 1968-08-19 Mehrschichtiges, metallisiertes, auf der Oberfläche eines planaren Halbleiterkörpers angeordnetes Verbindungs- und Anschlussnetz

Country Status (7)

Country Link
US (1) US3461357A (de)
CH (1) CH481487A (de)
DE (1) DE1764951B1 (de)
FR (1) FR1578564A (de)
GB (1) GB1233466A (de)
NL (1) NL6812711A (de)
SE (1) SE351748B (de)

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US3838442A (en) * 1970-04-15 1974-09-24 Ibm Semiconductor structure having metallization inlaid in insulating layers and method for making same
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US4005472A (en) * 1975-05-19 1977-01-25 National Semiconductor Corporation Method for gold plating of metallic layers on semiconductive devices
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JPS6136946A (ja) * 1984-07-30 1986-02-21 Nec Corp 半導体装置
US4788767A (en) * 1987-03-11 1988-12-06 International Business Machines Corporation Method for mounting a flexible film semiconductor chip carrier on a circuitized substrate
US5170931A (en) * 1987-03-11 1992-12-15 International Business Machines Corporation Method and apparatus for mounting a flexible film semiconductor chip carrier on a circuitized substrate
US5159535A (en) * 1987-03-11 1992-10-27 International Business Machines Corporation Method and apparatus for mounting a flexible film semiconductor chip carrier on a circuitized substrate
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US5281684A (en) * 1992-04-30 1994-01-25 Motorola, Inc. Solder bumping of integrated circuit die
US5767580A (en) * 1993-04-30 1998-06-16 Lsi Logic Corporation Systems having shaped, self-aligning micro-bump structures
US5477086A (en) * 1993-04-30 1995-12-19 Lsi Logic Corporation Shaped, self-aligning micro-bump structures
US5468984A (en) * 1994-11-02 1995-11-21 Texas Instruments Incorporated ESD protection structure using LDMOS diodes with thick copper interconnect
US6388203B1 (en) 1995-04-04 2002-05-14 Unitive International Limited Controlled-shaped solder reservoirs for increasing the volume of solder bumps, and structures formed thereby
WO1996031905A1 (en) 1995-04-05 1996-10-10 Mcnc A solder bump structure for a microelectronic substrate
US5789271A (en) * 1996-03-18 1998-08-04 Micron Technology, Inc. Method for fabricating microbump interconnect for bare semiconductor dice
US6078100A (en) 1999-01-13 2000-06-20 Micron Technology, Inc. Utilization of die repattern layers for die internal connections
JP4372943B2 (ja) 1999-02-23 2009-11-25 株式会社半導体エネルギー研究所 半導体装置およびその作製方法
US6710446B2 (en) * 1999-12-30 2004-03-23 Renesas Technology Corporation Semiconductor device comprising stress relaxation layers and method for manufacturing the same
JP3568869B2 (ja) * 2000-02-28 2004-09-22 シャープ株式会社 半導体集積回路装置及びその製造方法
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US6577002B1 (en) * 2001-11-29 2003-06-10 Sun Microsystems, Inc. 180 degree bump placement layout for an integrated circuit power grid
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Publication number Publication date
FR1578564A (de) 1969-08-14
DE1764951B1 (de) 1972-03-16
NL6812711A (de) 1969-03-18
SE351748B (de) 1972-12-04
US3461357A (en) 1969-08-12
GB1233466A (de) 1971-05-26

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