DE102020132231A1 - Mikroelektronisches bauteil, das geformte bereiche mit through-mold-vias aufweist - Google Patents

Mikroelektronisches bauteil, das geformte bereiche mit through-mold-vias aufweist Download PDF

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Publication number
DE102020132231A1
DE102020132231A1 DE102020132231.3A DE102020132231A DE102020132231A1 DE 102020132231 A1 DE102020132231 A1 DE 102020132231A1 DE 102020132231 A DE102020132231 A DE 102020132231A DE 102020132231 A1 DE102020132231 A1 DE 102020132231A1
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Prior art keywords
substrate
die
microelectronic
tsv
molding material
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DE102020132231.3A
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German (de)
English (en)
Inventor
Sanka Ganesan
Ram Viswanath
Xavier Francois Brun
Tarek A. Ibrahim
Jason M. Gamba
Manish Dubey
Robert Alan May
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Intel Corp
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Intel Corp
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    • H10W20/00Interconnections in chips, wafers or substrates
    • H10W20/40Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
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    • H10W70/60Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
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    • H10P72/70Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping
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    • H10W20/41Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/42Vias, e.g. via plugs
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    • H10W20/41Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
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    • H10W70/095Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers of vias therein
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    • H10W70/614Insulating or insulated package substrates; Interposers; Redistribution layers for connecting multiple chips together the multiple chips being integrally enclosed
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    • H10W70/618Insulating or insulated package substrates; Interposers; Redistribution layers for connecting multiple chips together package substrates, interposers or redistribution layers combined with bridge chips the bridge chips being embedded in the package substrates, interposers or redistribution layers
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    • H10W70/62Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
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    • H10W74/129Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed forming a chip-scale package [CSP]
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    • H10P72/7424Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support used as a support during the manufacture of self-supporting substrates
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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
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DE102020132231.3A 2020-03-25 2020-12-03 Mikroelektronisches bauteil, das geformte bereiche mit through-mold-vias aufweist Pending DE102020132231A1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US16/829,396 2020-03-25
US16/829,396 US11302643B2 (en) 2020-03-25 2020-03-25 Microelectronic component having molded regions with through-mold vias

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DE102020132231A1 true DE102020132231A1 (de) 2021-09-30

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US (6) US11302643B2 (https=)
JP (2) JP7458969B2 (https=)
KR (2) KR102772133B1 (https=)
CN (1) CN113451287A (https=)
DE (1) DE102020132231A1 (https=)

Families Citing this family (30)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11488918B2 (en) * 2018-10-31 2022-11-01 Intel Corporation Surface finishes with low rBTV for fine and mixed bump pitch architectures
US11854935B2 (en) 2020-02-19 2023-12-26 Intel Corporation Enhanced base die heat path using through-silicon vias
US11417819B2 (en) * 2020-04-27 2022-08-16 Microsoft Technology Licensing, Llc Forming a bumpless superconductor device by bonding two substrates via a dielectric layer
US11233035B2 (en) * 2020-05-28 2022-01-25 Taiwan Semiconductor Manufacturing Company, Ltd. Package structure and method of manufacturing the same
KR102883706B1 (ko) * 2020-06-30 2025-11-11 삼성전자주식회사 반도체 패키지
US11532582B2 (en) * 2020-08-25 2022-12-20 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device package and method of manufacture
TWI778406B (zh) * 2020-08-26 2022-09-21 矽品精密工業股份有限公司 電子封裝件及其製法
KR102816598B1 (ko) * 2020-09-04 2025-06-04 삼성전자주식회사 반도체 패키지 및 그 제조 방법
US11482497B2 (en) * 2021-01-14 2022-10-25 Taiwan Semiconductor Manufacturing Company, Ltd. Package structure including a first die and a second die and a bridge die and method of forming the package structure
US11664301B2 (en) * 2021-03-18 2023-05-30 Advanced Semiconductor Engineering, Inc. Semiconductor device package
US11817436B2 (en) * 2021-06-28 2023-11-14 Advanced Micro Devices, Inc. Common cooling solution for multiple packages
KR20230033115A (ko) * 2021-08-27 2023-03-08 삼성전자주식회사 반도체 패키지
US11823973B2 (en) * 2021-10-15 2023-11-21 STATS ChipPAC Pte. Ltd. Package with compartmentalized lid for heat spreader and EMI shield
US12463156B2 (en) * 2021-11-10 2025-11-04 Intel Corporation Packaging architectures for sub-terahertz radio frequency devices
US12046530B2 (en) * 2021-12-21 2024-07-23 Qualcomm Incorporated Thermal bridge interposer structure
US20230361068A1 (en) * 2022-05-03 2023-11-09 Taiwan Semiconductor Manufacturing Co. Ltd. Packaged Semiconductor Devices and Methods of Forming the Same
US20240014174A1 (en) * 2022-07-05 2024-01-11 Global Unichip Corporation Interface for a semiconductor chip with adaptive via region arrangement and semiconductor device with stacked semiconductor chips
CN114883279B (zh) * 2022-07-12 2022-10-25 深圳市冠禹半导体有限公司 一种氮化镓器件的封装方法
US20240038616A1 (en) * 2022-07-26 2024-02-01 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor package and manufacturing method thereof
US20240063127A1 (en) * 2022-08-16 2024-02-22 Intel Corporation Conformable die bond film (dbf) in glass cavity
US12538841B2 (en) * 2022-08-19 2026-01-27 Intel Corporation Quasi-monolithic die architectures
US12550781B2 (en) 2022-08-19 2026-02-10 Intel Corporation Template structure for quasi-monolithic die architectures
US20240071848A1 (en) * 2022-08-25 2024-02-29 Intel Corporation Through glass vias (tgvs) in glass core substrates
CN116130456A (zh) * 2022-09-14 2023-05-16 珠海越亚半导体股份有限公司 一种芯片高密度互连封装结构及其制作方法
CN118610193A (zh) * 2023-03-06 2024-09-06 华为技术有限公司 桥接芯片、芯片封装结构及制作方法、电子设备
WO2024210478A1 (ko) * 2023-04-04 2024-10-10 하나 마이크론(주) 반도체 패키지 및 그 제조방법
US20240379500A1 (en) * 2023-05-11 2024-11-14 Taiwan Semiconductor Manufacturing Company, Ltd. Through substrate via landing on front end of line structure
US20250046668A1 (en) * 2023-07-31 2025-02-06 Texas Instruments Incorporated Encapsulated wcsp with thermal pad for efficient heat dissipation
CN118315381B (zh) * 2024-04-10 2024-10-22 西安交通大学 一种柔性氮化镓功率模块及封装方法
JP2025181461A (ja) * 2024-05-31 2025-12-11 アオイ電子株式会社 半導体装置および半導体装置の製造方法

Family Cites Families (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3892774B2 (ja) * 2002-08-13 2007-03-14 富士通株式会社 半導体装置の製造方法
US7262074B2 (en) 2002-07-08 2007-08-28 Micron Technology, Inc. Methods of fabricating underfilled, encapsulated semiconductor die assemblies
JP4581768B2 (ja) 2005-03-16 2010-11-17 ソニー株式会社 半導体装置の製造方法
JP4208020B2 (ja) * 2007-04-13 2009-01-14 ダイキン工業株式会社 多翼ファンの羽根車
TWI543307B (zh) * 2012-09-27 2016-07-21 欣興電子股份有限公司 封裝載板與晶片封裝結構
US8901748B2 (en) 2013-03-14 2014-12-02 Intel Corporation Direct external interconnect for embedded interconnect bridge package
US9275955B2 (en) 2013-12-18 2016-03-01 Intel Corporation Integrated circuit package with embedded bridge
US9542522B2 (en) 2014-09-19 2017-01-10 Intel Corporation Interconnect routing configurations and associated techniques
CN105789058A (zh) * 2015-01-14 2016-07-20 钰桥半导体股份有限公司 中介层嵌置于加强层中的线路板及其制作方法
US9437536B1 (en) * 2015-05-08 2016-09-06 Invensas Corporation Reversed build-up substrate for 2.5D
US9613942B2 (en) 2015-06-08 2017-04-04 Qualcomm Incorporated Interposer for a package-on-package structure
US10008439B2 (en) * 2015-07-09 2018-06-26 Avago Technologies General Ip (Singapore) Pte. Ltd. Thin recon interposer package without TSV for fine input/output pitch fan-out
US9368450B1 (en) * 2015-08-21 2016-06-14 Qualcomm Incorporated Integrated device package comprising bridge in litho-etchable layer
US10325855B2 (en) * 2016-03-18 2019-06-18 Qualcomm Incorporated Backside drill embedded die substrate
KR20180086804A (ko) * 2017-01-23 2018-08-01 앰코 테크놀로지 인코포레이티드 반도체 디바이스 및 그 제조 방법
US20180240778A1 (en) 2017-02-22 2018-08-23 Intel Corporation Embedded multi-die interconnect bridge with improved power delivery
US10373893B2 (en) * 2017-06-30 2019-08-06 Intel Corporation Embedded bridge with through-silicon vias
US10727198B2 (en) * 2017-06-30 2020-07-28 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor package and method manufacturing the same
US10510721B2 (en) * 2017-08-11 2019-12-17 Advanced Micro Devices, Inc. Molded chip combination
US10340253B2 (en) * 2017-09-26 2019-07-02 Taiwan Semiconductor Manufacturing Co., Ltd. Package structure and method of manufacturing the same
US10763239B2 (en) * 2017-10-27 2020-09-01 Taiwan Semiconductor Manufacturing Co., Ltd. Multi-chip wafer level packages and methods of forming the same
US10872862B2 (en) * 2018-03-29 2020-12-22 Taiwan Semiconductor Manufacturing Company, Ltd. Package structure having bridge structure for connection between semiconductor dies and method of fabricating the same
US10535608B1 (en) * 2018-07-24 2020-01-14 International Business Machines Corporation Multi-chip package structure having chip interconnection bridge which provides power connections between chip and package substrate

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