DE10133281A1 - Speichervorrichtung - Google Patents

Speichervorrichtung

Info

Publication number
DE10133281A1
DE10133281A1 DE2001133281 DE10133281A DE10133281A1 DE 10133281 A1 DE10133281 A1 DE 10133281A1 DE 2001133281 DE2001133281 DE 2001133281 DE 10133281 A DE10133281 A DE 10133281A DE 10133281 A1 DE10133281 A1 DE 10133281A1
Authority
DE
Germany
Prior art keywords
bit line
write
transistor
line
write data
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
DE2001133281
Other languages
German (de)
English (en)
Inventor
Tatsuya Kunikiyo
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Publication of DE10133281A1 publication Critical patent/DE10133281A1/de
Ceased legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/16—Multiple access memory array, e.g. addressing one storage element via at least two independent addressing line groups
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Static Random-Access Memory (AREA)
DE2001133281 2000-07-10 2001-07-09 Speichervorrichtung Ceased DE10133281A1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2000207848 2000-07-10
JP2001148893A JP4748877B2 (ja) 2000-07-10 2001-05-18 記憶装置

Publications (1)

Publication Number Publication Date
DE10133281A1 true DE10133281A1 (de) 2002-01-31

Family

ID=26595666

Family Applications (1)

Application Number Title Priority Date Filing Date
DE2001133281 Ceased DE10133281A1 (de) 2000-07-10 2001-07-09 Speichervorrichtung

Country Status (4)

Country Link
JP (1) JP4748877B2 (enExample)
CN (1) CN1162914C (enExample)
DE (1) DE10133281A1 (enExample)
TW (1) TW523742B (enExample)

Cited By (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2011133356A1 (en) * 2010-04-23 2011-10-27 Advanced Micro Devices, Inc. 10t sram for graphics processing
GB2510828A (en) * 2013-02-13 2014-08-20 Surecore Ltd Single wordline low-power SRAM cells
EP3552206A4 (en) * 2016-12-06 2020-07-22 GSI Technology Inc. COMPUTING MEMORY CELL AND PROCESSING NETWORK DEVICE USING MEMORY CELLS
US10770133B1 (en) 2016-12-06 2020-09-08 Gsi Technology, Inc. Read and write data processing circuits and methods associated with computational memory cells that provides write inhibits and read bit line pre-charge inhibits
US10847213B1 (en) 2016-12-06 2020-11-24 Gsi Technology, Inc. Write data processing circuits and methods associated with computational memory cells
US10847212B1 (en) 2016-12-06 2020-11-24 Gsi Technology, Inc. Read and write data processing circuits and methods associated with computational memory cells using two read multiplexers
US10854284B1 (en) 2016-12-06 2020-12-01 Gsi Technology, Inc. Computational memory cell and processing array device with ratioless write port
US10860320B1 (en) 2016-12-06 2020-12-08 Gsi Technology, Inc. Orthogonal data transposition system and method during data transfers to/from a processing array
US10877731B1 (en) 2019-06-18 2020-12-29 Gsi Technology, Inc. Processing array device that performs one cycle full adder operation and bit line read/write logic features
US10891076B1 (en) 2016-12-06 2021-01-12 Gsi Technology, Inc. Results processing circuits and methods associated with computational memory cells
US10930341B1 (en) 2019-06-18 2021-02-23 Gsi Technology, Inc. Processing array device that performs one cycle full adder operation and bit line read/write logic features
US10943648B1 (en) 2016-12-06 2021-03-09 Gsi Technology, Inc. Ultra low VDD memory cell with ratioless write port
US10958272B2 (en) 2019-06-18 2021-03-23 Gsi Technology, Inc. Computational memory cell and processing array device using complementary exclusive or memory cells
US10998040B2 (en) 2016-12-06 2021-05-04 Gsi Technology, Inc. Computational memory cell and processing array device using the memory cells for XOR and XNOR computations
US11205476B1 (en) 2016-12-06 2021-12-21 Gsi Technology, Inc. Read data processing circuits and methods associated with computational memory cells
US11227653B1 (en) 2016-12-06 2022-01-18 Gsi Technology, Inc. Storage array circuits and methods for computational memory cells

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102004041331B4 (de) * 2004-08-26 2007-05-10 Infineon Technologies Ag Codesender, insbesondere zur Verwendung in einem Speichercontroller
JP2006236443A (ja) * 2005-02-23 2006-09-07 Seiko Epson Corp 強誘電体メモリ装置
JP2007172813A (ja) * 2005-11-25 2007-07-05 Semiconductor Energy Lab Co Ltd 半導体記憶装置及び半導体記憶装置の動作方法
JP4877094B2 (ja) * 2007-06-22 2012-02-15 日本テキサス・インスツルメンツ株式会社 半導体装置、半導体メモリ装置及び半導体メモリセル
JP5282430B2 (ja) * 2008-03-27 2013-09-04 富士通株式会社 半導体記憶装置
KR100953055B1 (ko) * 2008-05-20 2010-04-15 주식회사 하이닉스반도체 불휘발성 메모리 소자의 동작 방법
US7859919B2 (en) * 2008-08-27 2010-12-28 Freescale Semiconductor, Inc. Memory device and method thereof
US8111542B2 (en) * 2008-11-19 2012-02-07 Taiwan Semiconductor Manufacturing Co., Ltd. 8T low leakage SRAM cell
TWI410971B (zh) * 2009-12-01 2013-10-01 Faraday Tech Corp 靜態隨機存取記憶體
US8779488B2 (en) 2011-04-15 2014-07-15 Semiconductor Energy Laboratory Co., Ltd. Semiconductor memory device
GB2508221B (en) 2012-11-26 2015-02-25 Surecore Ltd Low-Power SRAM Cells

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Publication number Priority date Publication date Assignee Title
JPS563838Y2 (enExample) * 1974-09-19 1981-01-28
JPS5464433A (en) * 1977-10-31 1979-05-24 Nec Corp Memory cell
JPS608553A (ja) * 1983-06-27 1985-01-17 Isuzu Motors Ltd 自動クラツチの制御方法
JPH0734311B2 (ja) * 1986-01-21 1995-04-12 株式会社東芝 メモリセル
JP2743526B2 (ja) * 1989-10-23 1998-04-22 日本電気株式会社 レジスタ回路
JPH04298887A (ja) * 1991-03-26 1992-10-22 Nippon Telegr & Teleph Corp <Ntt> メモリ回路
JPH04372793A (ja) * 1991-06-21 1992-12-25 Nippon Telegr & Teleph Corp <Ntt> メモリ回路
JPH10340584A (ja) * 1997-06-09 1998-12-22 Nec Corp 半導体記憶装置
JPH117775A (ja) * 1997-06-17 1999-01-12 Sony Corp 半導体記憶装置
JP3104671B2 (ja) * 1998-03-09 2000-10-30 株式会社日立製作所 半導体記憶装置

Cited By (27)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2011133356A1 (en) * 2010-04-23 2011-10-27 Advanced Micro Devices, Inc. 10t sram for graphics processing
US8456945B2 (en) 2010-04-23 2013-06-04 Advanced Micro Devices, Inc. 10T SRAM for graphics processing
GB2510828A (en) * 2013-02-13 2014-08-20 Surecore Ltd Single wordline low-power SRAM cells
GB2510828B (en) * 2013-02-13 2015-06-03 Surecore Ltd Single wordline low-power SRAM cells
US9627062B2 (en) 2013-02-13 2017-04-18 Surecore Limited SRAM cells
US11094374B1 (en) 2016-12-06 2021-08-17 Gsi Technology, Inc. Write data processing circuits and methods associated with computational memory cells
US11409528B2 (en) 2016-12-06 2022-08-09 Gsi Technology, Inc. Orthogonal data transposition system and method during data transfers to/from a processing array
US10847213B1 (en) 2016-12-06 2020-11-24 Gsi Technology, Inc. Write data processing circuits and methods associated with computational memory cells
US10847212B1 (en) 2016-12-06 2020-11-24 Gsi Technology, Inc. Read and write data processing circuits and methods associated with computational memory cells using two read multiplexers
US10854284B1 (en) 2016-12-06 2020-12-01 Gsi Technology, Inc. Computational memory cell and processing array device with ratioless write port
US10860320B1 (en) 2016-12-06 2020-12-08 Gsi Technology, Inc. Orthogonal data transposition system and method during data transfers to/from a processing array
US10860318B2 (en) 2016-12-06 2020-12-08 Gsi Technology, Inc. Computational memory cell and processing array device using memory cells
US11763881B2 (en) 2016-12-06 2023-09-19 Gsi Technology, Inc. Computational memory cell and processing array device using the memory cells for XOR and XNOR computations
US10891076B1 (en) 2016-12-06 2021-01-12 Gsi Technology, Inc. Results processing circuits and methods associated with computational memory cells
US11227653B1 (en) 2016-12-06 2022-01-18 Gsi Technology, Inc. Storage array circuits and methods for computational memory cells
US10943648B1 (en) 2016-12-06 2021-03-09 Gsi Technology, Inc. Ultra low VDD memory cell with ratioless write port
US10770133B1 (en) 2016-12-06 2020-09-08 Gsi Technology, Inc. Read and write data processing circuits and methods associated with computational memory cells that provides write inhibits and read bit line pre-charge inhibits
US10998040B2 (en) 2016-12-06 2021-05-04 Gsi Technology, Inc. Computational memory cell and processing array device using the memory cells for XOR and XNOR computations
EP3552206A4 (en) * 2016-12-06 2020-07-22 GSI Technology Inc. COMPUTING MEMORY CELL AND PROCESSING NETWORK DEVICE USING MEMORY CELLS
US11150903B2 (en) 2016-12-06 2021-10-19 Gsi Technology, Inc. Computational memory cell and processing array device using memory cells
US11194519B2 (en) 2016-12-06 2021-12-07 Gsi Technology, Inc. Results processing circuits and methods associated with computational memory cells
US11257540B2 (en) 2016-12-06 2022-02-22 Gsi Technology, Inc. Write data processing methods associated with computational memory cells
US11205476B1 (en) 2016-12-06 2021-12-21 Gsi Technology, Inc. Read data processing circuits and methods associated with computational memory cells
US10958272B2 (en) 2019-06-18 2021-03-23 Gsi Technology, Inc. Computational memory cell and processing array device using complementary exclusive or memory cells
US11194548B2 (en) 2019-06-18 2021-12-07 Gsi Technology, Inc. Processing array device that performs one cycle full adder operation and bit line read/write logic features
US10930341B1 (en) 2019-06-18 2021-02-23 Gsi Technology, Inc. Processing array device that performs one cycle full adder operation and bit line read/write logic features
US10877731B1 (en) 2019-06-18 2020-12-29 Gsi Technology, Inc. Processing array device that performs one cycle full adder operation and bit line read/write logic features

Also Published As

Publication number Publication date
JP2002093176A (ja) 2002-03-29
JP4748877B2 (ja) 2011-08-17
CN1341941A (zh) 2002-03-27
CN1162914C (zh) 2004-08-18
TW523742B (en) 2003-03-11

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Legal Events

Date Code Title Description
OP8 Request for examination as to paragraph 44 patent law
8131 Rejection