DE10043183A1 - Halbleitervorrichtung und Herstellungsvorrichtung von einer Halbleitervorrichtung - Google Patents

Halbleitervorrichtung und Herstellungsvorrichtung von einer Halbleitervorrichtung

Info

Publication number
DE10043183A1
DE10043183A1 DE10043183A DE10043183A DE10043183A1 DE 10043183 A1 DE10043183 A1 DE 10043183A1 DE 10043183 A DE10043183 A DE 10043183A DE 10043183 A DE10043183 A DE 10043183A DE 10043183 A1 DE10043183 A1 DE 10043183A1
Authority
DE
Germany
Prior art keywords
insulation film
semiconductor layer
gate electrode
semiconductor
film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
DE10043183A
Other languages
German (de)
English (en)
Inventor
Yuuichi Hirano
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Publication of DE10043183A1 publication Critical patent/DE10043183A1/de
Ceased legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/673—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes
    • H10D30/6733—Multi-gate TFTs
    • H10D30/6734—Multi-gate TFTs having gate electrodes arranged on both top and bottom sides of the channel, e.g. dual-gate TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/201—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates the substrates comprising an insulating layer on a semiconductor body, e.g. SOI
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/19—Preparing inhomogeneous wafers
    • H10P90/1904—Preparing vertically inhomogeneous wafers
    • H10P90/1906—Preparing SOI wafers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H10W10/061—Manufacture or treatment using SOI processes together with lateral isolation, e.g. combinations of SOI and shallow trench isolations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/181—Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H10W10/011—Manufacture or treatment of isolation regions comprising dielectric materials
    • H10W10/012—Manufacture or treatment of isolation regions comprising dielectric materials using local oxidation of silicon [LOCOS]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/13—Isolation regions comprising dielectric materials formed using local oxidation of silicon [LOCOS], e.g. sealed interface localised oxidation [SILO] or side-wall mask isolation [SWAMI]

Landscapes

  • Thin Film Transistor (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
DE10043183A 1999-09-03 2000-09-01 Halbleitervorrichtung und Herstellungsvorrichtung von einer Halbleitervorrichtung Ceased DE10043183A1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP25047599A JP2001077368A (ja) 1999-09-03 1999-09-03 半導体装置及びその製造方法

Publications (1)

Publication Number Publication Date
DE10043183A1 true DE10043183A1 (de) 2001-04-12

Family

ID=17208415

Family Applications (1)

Application Number Title Priority Date Filing Date
DE10043183A Ceased DE10043183A1 (de) 1999-09-03 2000-09-01 Halbleitervorrichtung und Herstellungsvorrichtung von einer Halbleitervorrichtung

Country Status (4)

Country Link
US (2) US6252280B1 (https=)
JP (1) JP2001077368A (https=)
KR (1) KR100340395B1 (https=)
DE (1) DE10043183A1 (https=)

Families Citing this family (28)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6444432B1 (en) * 1997-06-13 2002-09-03 Alan M. Kleinfeld Method of detection of cardiac ischemia using fatty acid binding protein
JP2000243967A (ja) * 1999-02-22 2000-09-08 Sony Corp 半導体装置の製造方法
JP3716406B2 (ja) * 2000-02-08 2005-11-16 富士通株式会社 絶縁ゲート型半導体装置及びその製造方法
JP4698793B2 (ja) * 2000-04-03 2011-06-08 ルネサスエレクトロニクス株式会社 半導体装置
JP4988086B2 (ja) * 2000-06-13 2012-08-01 ルネサスエレクトロニクス株式会社 半導体装置及びその製造方法並びに抵抗器及び半導体素子
JP2002033484A (ja) * 2000-07-18 2002-01-31 Mitsubishi Electric Corp 半導体装置
JP3990858B2 (ja) * 2000-07-31 2007-10-17 株式会社東芝 半導体装置
JP2002185011A (ja) * 2000-12-19 2002-06-28 Seiko Epson Corp 半導体装置
JP2002299633A (ja) * 2001-04-03 2002-10-11 Sony Corp 電界効果型トランジスタ
TW200305976A (en) 2001-04-03 2003-11-01 Matsushita Electric Industrial Co Ltd Semiconductor device and method for fabricating the same
JP2003318405A (ja) 2002-04-25 2003-11-07 Mitsubishi Electric Corp 半導体装置およびその製造方法
US7196369B2 (en) * 2002-07-15 2007-03-27 Macronix International Co., Ltd. Plasma damage protection circuit for a semiconductor device
JP4294935B2 (ja) 2002-10-17 2009-07-15 株式会社ルネサステクノロジ 半導体装置
JP4154578B2 (ja) * 2002-12-06 2008-09-24 日本電気株式会社 半導体装置及びその製造方法
US6905919B2 (en) 2003-07-29 2005-06-14 Chartered Semiconductor Manufacturing Ltd. Method of forming a partially depleted silicon on insulator (PDSOI) transistor with a pad lock body extension
KR100706737B1 (ko) 2003-08-28 2007-04-12 가부시끼가이샤 르네사스 테크놀로지 반도체 기억 장치 및 그 제조 방법
JP2006049784A (ja) * 2003-08-28 2006-02-16 Renesas Technology Corp 半導体記憶装置及びその製造方法
JP2006054430A (ja) * 2004-07-12 2006-02-23 Renesas Technology Corp 半導体装置
KR100629264B1 (ko) 2004-07-23 2006-09-29 삼성전자주식회사 게이트 관통 바디 콘택을 갖는 반도체소자 및 그 제조방법
JP2006066691A (ja) 2004-08-27 2006-03-09 Renesas Technology Corp 半導体装置およびその製造方法
US7170816B2 (en) * 2004-12-16 2007-01-30 Macronix International Co., Ltd. Method and apparatus for passing charge from word lines during manufacture
JP5270876B2 (ja) * 2007-08-22 2013-08-21 セイコーインスツル株式会社 半導体装置
US7964897B2 (en) * 2008-07-22 2011-06-21 Honeywell International Inc. Direct contact to area efficient body tie process flow
US8680617B2 (en) * 2009-10-06 2014-03-25 International Business Machines Corporation Split level shallow trench isolation for area efficient body contacts in SOI MOSFETS
US8558960B2 (en) * 2010-09-13 2013-10-15 Semiconductor Energy Laboratory Co., Ltd. Liquid crystal display device and method for manufacturing the same
US9490249B2 (en) 2014-04-30 2016-11-08 Macronix International Co., Ltd. Antenna effect discharge circuit and manufacturing method
US10546929B2 (en) 2017-07-19 2020-01-28 Commissariat A L'energie Atomique Et Aux Energies Alternatives Optimized double-gate transistors and fabricating process
FR3069373A1 (fr) * 2017-07-19 2019-01-25 Commissariat A L'energie Atomique Et Aux Energies Alternatives Transistors double grilles optimises et procede de fabrication

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5559368A (en) * 1994-08-30 1996-09-24 The Regents Of The University Of California Dynamic threshold voltage mosfet having gate to body connection for ultra-low voltage operation
JPH0969610A (ja) * 1995-08-31 1997-03-11 Hitachi Ltd 集積半導体装置およびその製造方法
US5753955A (en) * 1996-12-19 1998-05-19 Honeywell Inc. MOS device having a gate to body connection with a body injection current limiting feature for use on silicon on insulator substrates
TW362258B (en) * 1998-03-20 1999-06-21 United Microelectronics Corp Silicon trench contact structure on the insulation layer
US6080612A (en) * 1998-05-20 2000-06-27 Sharp Laboratories Of America, Inc. Method of forming an ultra-thin SOI electrostatic discharge protection device
US6159807A (en) * 1998-09-21 2000-12-12 International Business Machines Corporation Self-aligned dynamic threshold CMOS device

Also Published As

Publication number Publication date
US20010029067A1 (en) 2001-10-11
US6252280B1 (en) 2001-06-26
US6337230B2 (en) 2002-01-08
KR20010030243A (ko) 2001-04-16
KR100340395B1 (ko) 2002-06-15
JP2001077368A (ja) 2001-03-23

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