DD152875A5 - Verfahren zum herstellen eines hochintegrierten festwertspeichers - Google Patents
Verfahren zum herstellen eines hochintegrierten festwertspeichers Download PDFInfo
- Publication number
- DD152875A5 DD152875A5 DD80223393A DD22339380A DD152875A5 DD 152875 A5 DD152875 A5 DD 152875A5 DD 80223393 A DD80223393 A DD 80223393A DD 22339380 A DD22339380 A DD 22339380A DD 152875 A5 DD152875 A5 DD 152875A5
- Authority
- DD
- German Democratic Republic
- Prior art keywords
- substrate
- region
- impurities
- gate electrode
- diffusion
- Prior art date
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 26
- 238000003860 storage Methods 0.000 title description 3
- 239000000758 substrate Substances 0.000 claims abstract description 36
- 230000015654 memory Effects 0.000 claims abstract description 35
- 238000009792 diffusion process Methods 0.000 claims abstract description 29
- 239000012535 impurity Substances 0.000 claims abstract description 26
- 238000000034 method Methods 0.000 claims abstract description 14
- 230000005669 field effect Effects 0.000 claims abstract description 7
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical group [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 9
- 229910052796 boron Inorganic materials 0.000 claims description 9
- 229910052785 arsenic Inorganic materials 0.000 claims description 6
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical group [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 claims description 6
- 238000010438 heat treatment Methods 0.000 claims description 3
- 238000011109 contamination Methods 0.000 claims description 2
- 238000002360 preparation method Methods 0.000 claims 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 8
- 230000010354 integration Effects 0.000 description 8
- 238000005468 ion implantation Methods 0.000 description 5
- 235000012239 silicon dioxide Nutrition 0.000 description 4
- 239000000377 silicon dioxide Substances 0.000 description 4
- 150000002500 ions Chemical class 0.000 description 3
- 238000002955 isolation Methods 0.000 description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
- 229920005591 polysilicon Polymers 0.000 description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 239000007943 implant Substances 0.000 description 2
- 238000002513 implantation Methods 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- HEFNNWSXXWATRW-UHFFFAOYSA-N Ibuprofen Chemical compound CC(C)CC1=CC=C(C(C)C(O)=O)C=C1 HEFNNWSXXWATRW-UHFFFAOYSA-N 0.000 description 1
- 239000000356 contaminant Substances 0.000 description 1
- 239000004148 curcumin Substances 0.000 description 1
- 230000006735 deficit Effects 0.000 description 1
- 238000007599 discharging Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
- G11C11/5692—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency read-only digital stores using storage elements with more than two stable states
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
- G11C17/08—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards using semiconductor devices, e.g. bipolar elements
- G11C17/10—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards using semiconductor devices, e.g. bipolar elements in which contents are determined during manufacturing by a predetermined arrangement of coupling elements, e.g. mask-programmable ROM
- G11C17/12—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards using semiconductor devices, e.g. bipolar elements in which contents are determined during manufacturing by a predetermined arrangement of coupling elements, e.g. mask-programmable ROM using field-effect devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
- H01L21/225—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a solid phase, e.g. a doped oxide layer
- H01L21/2251—Diffusion into or out of group IV semiconductors
- H01L21/2252—Diffusion into or out of group IV semiconductors using predeposition of impurities into the semiconductor surface, e.g. from a gaseous phase
- H01L21/2253—Diffusion into or out of group IV semiconductors using predeposition of impurities into the semiconductor surface, e.g. from a gaseous phase by ion implantation
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B20/00—Read-only memory [ROM] devices
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B20/00—Read-only memory [ROM] devices
- H10B20/27—ROM only
- H10B20/30—ROM only having the source region and the drain region on the same level, e.g. lateral transistors
- H10B20/38—Doping programmed, e.g. mask ROM
- H10B20/387—Source region or drain region doping programmed
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Semiconductor Memories (AREA)
- Semiconductor Integrated Circuits (AREA)
- Non-Volatile Memory (AREA)
- Bipolar Transistors (AREA)
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US06/068,282 US4282646A (en) | 1979-08-20 | 1979-08-20 | Method of making a transistor array |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| DD152875A5 true DD152875A5 (de) | 1981-12-09 |
Family
ID=22081587
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| DD80223393A DD152875A5 (de) | 1979-08-20 | 1980-08-19 | Verfahren zum herstellen eines hochintegrierten festwertspeichers |
Country Status (7)
| Country | Link |
|---|---|
| US (1) | US4282646A (fr) |
| EP (1) | EP0024311B1 (fr) |
| JP (1) | JPS5630765A (fr) |
| AT (1) | ATE20507T1 (fr) |
| DD (1) | DD152875A5 (fr) |
| DE (1) | DE3071648D1 (fr) |
| IT (1) | IT1150032B (fr) |
Families Citing this family (30)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4402761A (en) * | 1978-12-15 | 1983-09-06 | Raytheon Company | Method of making self-aligned gate MOS device having small channel lengths |
| JPS5826829B2 (ja) * | 1979-08-30 | 1983-06-06 | 富士通株式会社 | ダイナミックメモリセルの製造方法 |
| US4514897A (en) * | 1979-09-04 | 1985-05-07 | Texas Instruments Incorporated | Electrically programmable floating gate semiconductor memory device |
| DE2947350A1 (de) * | 1979-11-23 | 1981-05-27 | Siemens AG, 1000 Berlin und 8000 München | Verfahren zum herstellen von mnos-speichertransistoren mit sehr kurzer kanallaenge in silizium-gate-technologie |
| US4883543A (en) * | 1980-06-05 | 1989-11-28 | Texas Instruments Incroporated | Shielding for implant in manufacture of dynamic memory |
| US4329773A (en) * | 1980-12-10 | 1982-05-18 | International Business Machines Corp. | Method of making low leakage shallow junction IGFET devices |
| US4366613A (en) * | 1980-12-17 | 1983-01-04 | Ibm Corporation | Method of fabricating an MOS dynamic RAM with lightly doped drain |
| US4380866A (en) * | 1981-05-04 | 1983-04-26 | Motorola, Inc. | Method of programming ROM by offset masking of selected gates |
| US4599118A (en) * | 1981-12-30 | 1986-07-08 | Mostek Corporation | Method of making MOSFET by multiple implantations followed by a diffusion step |
| USRE32800E (en) * | 1981-12-30 | 1988-12-13 | Sgs-Thomson Microelectronics, Inc. | Method of making mosfet by multiple implantations followed by a diffusion step |
| US4536944A (en) * | 1982-12-29 | 1985-08-27 | International Business Machines Corporation | Method of making ROM/PLA semiconductor device by late stage personalization |
| JPS59148360A (ja) * | 1983-02-14 | 1984-08-25 | Fujitsu Ltd | 半導体記憶装置及びその製造方法 |
| JPS6030170A (ja) * | 1983-07-29 | 1985-02-15 | Hitachi Ltd | 高集積読み出し専用メモリ |
| JPS62140469U (fr) * | 1986-02-28 | 1987-09-04 | ||
| JPS62203069A (ja) * | 1986-03-03 | 1987-09-07 | Nissin Electric Co Ltd | 耐電圧試験装置 |
| US4745079A (en) * | 1987-03-30 | 1988-05-17 | Motorola, Inc. | Method for fabricating MOS transistors having gates with different work functions |
| JP2530054B2 (ja) * | 1990-08-28 | 1996-09-04 | 株式会社東芝 | 半導体記憶装置の製造方法 |
| US6964890B1 (en) * | 1992-03-17 | 2005-11-15 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method for forming the same |
| JP3202784B2 (ja) * | 1992-04-13 | 2001-08-27 | 三菱電機株式会社 | マスクｒｏｍ半導体装置およびその製造方法 |
| US5432103A (en) * | 1992-06-22 | 1995-07-11 | National Semiconductor Corporation | Method of making semiconductor ROM cell programmed using source mask |
| FR2737597B1 (fr) | 1995-07-31 | 1997-08-29 | Sgs Thomson Microelectronics | Procede de programmation d'une cellule de memoire morte et memoire associee |
| FR2738089B1 (fr) * | 1995-08-24 | 1997-10-31 | Sgs Thomson Microelectronics | Dispositif de correction de linearite de rampes d'un signal en dents de scie et generateur d'un tel signal |
| JPH10125906A (ja) * | 1996-10-18 | 1998-05-15 | Rohm Co Ltd | 半導体装置及びその製造方法 |
| DE19815873A1 (de) * | 1998-04-08 | 1999-10-14 | Siemens Ag | Verfahren zur Herstellung einer Halbleiter-Speichervorrichtung |
| EP0957521A1 (fr) | 1998-05-11 | 1999-11-17 | STMicroelectronics S.r.l. | Matrice de mémoire à semiconducteur ayant des cellules ROM réalisée par un procédé de fabrication auto-aligné des sources (SAS), et procédé de fabrication correspondant |
| DE19929675A1 (de) * | 1999-06-28 | 2001-04-12 | Infineon Technologies Ag | Verfahren zur Herstellung von ROM-Speicherzellen |
| US6927993B2 (en) * | 2003-08-14 | 2005-08-09 | Silicon Storage Technology, Inc. | Multi-bit ROM cell, for storing on of N>4 possible states and having bi-directional read, an array of such cells |
| US7012310B2 (en) * | 2003-08-14 | 2006-03-14 | Silcon Storage Technology, Inc. | Array of multi-bit ROM cells with each cell having bi-directional read and a method for making the array |
| US6870233B2 (en) * | 2003-08-14 | 2005-03-22 | Silicon Storage Technology, Inc. | Multi-bit ROM cell with bi-directional read and a method for making thereof |
| US7001811B2 (en) * | 2003-12-31 | 2006-02-21 | Intel Corporation | Method for making memory cell without halo implant |
Family Cites Families (18)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| USB421061I5 (fr) * | 1964-12-24 | |||
| GB1316555A (fr) * | 1969-08-12 | 1973-05-09 | ||
| US3996655A (en) * | 1973-12-14 | 1976-12-14 | Texas Instruments Incorporated | Processes of forming insulated gate field effect transistors with channel lengths of one micron in integrated circuits with component isolated and product |
| US3914855A (en) * | 1974-05-09 | 1975-10-28 | Bell Telephone Labor Inc | Methods for making MOS read-only memories |
| US4096522A (en) * | 1974-09-26 | 1978-06-20 | Tokyo Shibaura Electric Co., Ltd. | Monolithic semiconductor mask programmable ROM and a method for manufacturing the same |
| US4045811A (en) * | 1975-08-04 | 1977-08-30 | Rca Corporation | Semiconductor integrated circuit device including an array of insulated gate field effect transistors |
| US4059826A (en) * | 1975-12-29 | 1977-11-22 | Texas Instruments Incorporated | Semiconductor memory array with field effect transistors programmable by alteration of threshold voltage |
| US4035820A (en) * | 1975-12-29 | 1977-07-12 | Texas Instruments Incorporated | Adjustment of avalanche voltage in DIFMOS memory devices by control of impurity doping |
| GB1569897A (en) * | 1975-12-31 | 1980-06-25 | Ibm | Field effect transistor |
| JPS5333076A (en) * | 1976-09-09 | 1978-03-28 | Toshiba Corp | Production of mos type integrated circuit |
| US4232439A (en) * | 1976-11-30 | 1980-11-11 | Vlsi Technology Research Association | Masking technique usable in manufacturing semiconductor devices |
| JPS5368079A (en) * | 1976-11-30 | 1978-06-17 | Cho Lsi Gijutsu Kenkyu Kumiai | Short channel mos transistor and method of producing same |
| US4161039A (en) * | 1976-12-15 | 1979-07-10 | Siemens Aktiengesellschaft | N-Channel storage FET |
| US4142926A (en) * | 1977-02-24 | 1979-03-06 | Intel Corporation | Self-aligning double polycrystalline silicon etching process |
| US4173818A (en) * | 1978-05-30 | 1979-11-13 | International Business Machines Corporation | Method for fabricating transistor structures having very short effective channels |
| US4208780A (en) * | 1978-08-03 | 1980-06-24 | Rca Corporation | Last-stage programming of semiconductor integrated circuits including selective removal of passivation layer |
| US4209349A (en) * | 1978-11-03 | 1980-06-24 | International Business Machines Corporation | Method for forming a narrow dimensioned mask opening on a silicon body utilizing reactive ion etching |
| US4214359A (en) * | 1978-12-07 | 1980-07-29 | Bell Telephone Laboratories, Incorporated | MOS Devices having buried terminal zones under local oxide regions |
-
1979
- 1979-08-20 US US06/068,282 patent/US4282646A/en not_active Expired - Lifetime
-
1980
- 1980-06-18 JP JP8150180A patent/JPS5630765A/ja active Pending
- 1980-07-24 AT AT80104358T patent/ATE20507T1/de not_active IP Right Cessation
- 1980-07-24 DE DE8080104358T patent/DE3071648D1/de not_active Expired
- 1980-07-24 EP EP80104358A patent/EP0024311B1/fr not_active Expired
- 1980-07-25 IT IT23688/80A patent/IT1150032B/it active
- 1980-08-19 DD DD80223393A patent/DD152875A5/de unknown
Also Published As
| Publication number | Publication date |
|---|---|
| IT8023688A1 (it) | 1982-01-25 |
| IT1150032B (it) | 1986-12-10 |
| US4282646A (en) | 1981-08-11 |
| EP0024311A3 (en) | 1982-09-01 |
| JPS5630765A (en) | 1981-03-27 |
| IT8023688A0 (it) | 1980-07-25 |
| DE3071648D1 (en) | 1986-07-24 |
| EP0024311A2 (fr) | 1981-03-04 |
| EP0024311B1 (fr) | 1986-06-18 |
| ATE20507T1 (de) | 1986-07-15 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| DD152875A5 (de) | Verfahren zum herstellen eines hochintegrierten festwertspeichers | |
| EP0025130B1 (fr) | Mémoire morte intégrée très dense | |
| DE2841453C2 (de) | Halbleiterspeicherzelle | |
| DE2552644C2 (de) | Integrierter Halbleiter-Festspeicher und Verfahren zu seiner Herstellung | |
| DE3033333A1 (de) | Elektrisch programmierbare halbleiterspeichervorrichtung | |
| DE2654728A1 (de) | Programmierbarer festwertspeicher und verfahren zu seiner herstellung | |
| DE69013094T2 (de) | Nichtflüchtige Halbleiterspeicheranordnung und Verfahren zu ihrer Herstellung. | |
| DE2630571B2 (de) | Ein-Transistor-Speicherzelle mit in V-MOS-Technik | |
| DE2756855A1 (de) | Verfahren zum herstellen einer matrix aus speicherzellen mit hoher speicherkapazitaet | |
| DE2547828A1 (de) | Halbleiter-speicherelement und verfahren zur herstellung desselben | |
| DE68909350T2 (de) | Hochintegrierte EPROM-Speicheranordnung mit einer quadratischen Gitterorganisation und mit einem verbesserten Kopplungsfaktor. | |
| DE19611438A1 (de) | EEPROM Flashzelle sowie Verfahren zu deren Herstellung | |
| DE3787687T2 (de) | Halbleiterspeicher. | |
| DE2720533C2 (fr) | ||
| DE3139846C2 (fr) | ||
| DE2823854A1 (de) | Integrierte halbleiterspeichervorrichtung | |
| DE3140268A1 (de) | Halbleiteranordnung mit mindestens einem feldeffekttransistor und verfahren zu ihrer herstellung | |
| DE3134233C2 (fr) | ||
| DE2937952C2 (de) | Nichtflüchtige Speicheranordnung | |
| DE2703871C2 (de) | Halbleiterspeicher mit wenigstens einem V-MOS-Transistor | |
| DE2743299A1 (de) | Ladungskopplungsanordnung | |
| EP0021218B1 (fr) | Cellule à mémoire semiconductrice dynamique et procédé pour sa fabrication | |
| DE68911418T2 (de) | Hochintegrierte EPROM-Speicheranordnung mit einem grossen Kopplungsfaktor. | |
| DE2751591A1 (de) | Dynamische speichereinrichtung | |
| DE2713479A1 (de) | Verfahren zur herstellung von integrierten schaltkreisen |