CN1971903B - 具有对准标记层的半导体器件及其制造方法 - Google Patents
具有对准标记层的半导体器件及其制造方法 Download PDFInfo
- Publication number
- CN1971903B CN1971903B CN2006101486633A CN200610148663A CN1971903B CN 1971903 B CN1971903 B CN 1971903B CN 2006101486633 A CN2006101486633 A CN 2006101486633A CN 200610148663 A CN200610148663 A CN 200610148663A CN 1971903 B CN1971903 B CN 1971903B
- Authority
- CN
- China
- Prior art keywords
- layer
- metal layer
- alignment mark
- pad electrode
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W46/00—Marks applied to devices, e.g. for alignment or identification
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
- H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W46/00—Marks applied to devices, e.g. for alignment or identification
- H10W46/301—Marks applied to devices, e.g. for alignment or identification for alignment
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W46/00—Marks applied to devices, e.g. for alignment or identification
- H10W46/601—Marks applied to devices, e.g. for alignment or identification for use after dicing
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W46/00—Marks applied to devices, e.g. for alignment or identification
- H10W46/601—Marks applied to devices, e.g. for alignment or identification for use after dicing
- H10W46/603—Formed on wafers or substrates before dicing and remaining on chips after dicing
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/01—Manufacture or treatment
- H10W72/012—Manufacture or treatment of bump connectors, dummy bumps or thermal bumps
- H10W72/01251—Changing the shapes of bumps
- H10W72/01255—Changing the shapes of bumps by using masks
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/01—Manufacture or treatment
- H10W72/019—Manufacture or treatment of bond pads
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/071—Connecting or disconnecting
- H10W72/072—Connecting or disconnecting of bump connectors
- H10W72/07221—Aligning
- H10W72/07223—Active alignment, e.g. using optical alignment using marks or sensors
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/071—Connecting or disconnecting
- H10W72/072—Connecting or disconnecting of bump connectors
- H10W72/07231—Techniques
- H10W72/07236—Soldering or alloying
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/071—Connecting or disconnecting
- H10W72/072—Connecting or disconnecting of bump connectors
- H10W72/07251—Connecting or disconnecting of bump connectors characterised by changes in properties of the bump connectors during connecting
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
- H10W72/241—Dispositions, e.g. layouts
- H10W72/242—Dispositions, e.g. layouts relative to the surface, e.g. recessed, protruding
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
- H10W72/251—Materials
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
- H10W72/251—Materials
- H10W72/252—Materials comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
- H10W72/29—Bond pads specially adapted therefor
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/90—Bond pads, in general
- H10W72/931—Shapes of bond pads
- H10W72/934—Cross-sectional shape, i.e. in side view
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/90—Bond pads, in general
- H10W72/941—Dispositions of bond pads
- H10W72/9415—Dispositions of bond pads relative to the surface, e.g. recessed, protruding
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S438/00—Semiconductor device manufacturing: process
- Y10S438/975—Substrate or mask aligning feature
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020050111994A KR100660893B1 (ko) | 2005-11-22 | 2005-11-22 | 정렬 마크막을 구비하는 반도체 소자 및 그 제조 방법 |
| KR111994/05 | 2005-11-22 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1971903A CN1971903A (zh) | 2007-05-30 |
| CN1971903B true CN1971903B (zh) | 2010-05-19 |
Family
ID=37815395
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2006101486633A Active CN1971903B (zh) | 2005-11-22 | 2006-11-22 | 具有对准标记层的半导体器件及其制造方法 |
Country Status (5)
| Country | Link |
|---|---|
| US (1) | US7482703B2 (https=) |
| JP (1) | JP2007142436A (https=) |
| KR (1) | KR100660893B1 (https=) |
| CN (1) | CN1971903B (https=) |
| DE (1) | DE102006056066A1 (https=) |
Families Citing this family (27)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8492263B2 (en) | 2007-11-16 | 2013-07-23 | Taiwan Semiconductor Manufacturing Company, Ltd. | Protected solder ball joints in wafer level chip-scale packaging |
| US20090174069A1 (en) * | 2008-01-04 | 2009-07-09 | National Semiconductor Corporation | I/o pad structure for enhancing solder joint reliability in integrated circuit devices |
| KR20090095076A (ko) * | 2008-03-04 | 2009-09-09 | 삼성전자주식회사 | 반도체 집적 회로 장치 및 그 제조 방법 |
| JP2010021293A (ja) * | 2008-07-09 | 2010-01-28 | Nec Electronics Corp | 半導体装置および半導体装置の製造方法 |
| CN101789391B (zh) * | 2009-01-23 | 2012-08-22 | 中芯国际集成电路制造(上海)有限公司 | 半导体装置及其制造方法 |
| JP2010225934A (ja) * | 2009-03-24 | 2010-10-07 | Mitsumi Electric Co Ltd | ウエハの製造方法 |
| US8299616B2 (en) * | 2010-01-29 | 2012-10-30 | Taiwan Semiconductor Manufacturing Company, Ltd. | T-shaped post for semiconductor devices |
| US8803319B2 (en) | 2010-02-11 | 2014-08-12 | Taiwan Semiconductor Manufacturing Company, Ltd. | Pillar structure having a non-planar surface for semiconductor devices |
| US8318596B2 (en) * | 2010-02-11 | 2012-11-27 | Taiwan Semiconductor Manufacturing Company, Ltd. | Pillar structure having a non-planar surface for semiconductor devices |
| CN102157497B (zh) * | 2011-01-26 | 2016-03-09 | 上海华虹宏力半导体制造有限公司 | 多层堆栈的半导体器件的结构及形成方法 |
| DE102011005642B4 (de) | 2011-03-16 | 2012-09-27 | GLOBALFOUNDRIES Dresden Module One Ltd. Liability Company & Co. KG | Verfahren zum Schutz von reaktiven Metalloberflächen von Halbleiterbauelementen während des Transports durch Bereitstellen einer zusätzlichen Schutzschicht |
| JP2013004572A (ja) * | 2011-06-13 | 2013-01-07 | Mitsubishi Electric Corp | 半導体装置の製造方法 |
| US9230932B2 (en) | 2012-02-09 | 2016-01-05 | Taiwan Semiconductor Manufacturing Company, Ltd. | Interconnect crack arrestor structure and methods |
| US9515036B2 (en) | 2012-04-20 | 2016-12-06 | Taiwan Semiconductor Manufacturing Company, Ltd. | Methods and apparatus for solder connections |
| CN103682085B (zh) * | 2012-09-20 | 2016-08-03 | 中芯国际集成电路制造(上海)有限公司 | 一种磁随机存取存储器及其制造方法 |
| CN103199084B (zh) * | 2013-03-08 | 2015-10-14 | 京东方科技集团股份有限公司 | 基板对位标记、基板及基板对位标记的制作方法 |
| US8987922B2 (en) | 2013-03-11 | 2015-03-24 | Taiwan Semiconductor Manufacturing Company, Ltd. | Methods and apparatus for wafer level packaging |
| US9355979B2 (en) | 2013-08-16 | 2016-05-31 | Taiwan Semiconductor Manufacturing Company, Ltd. | Alignment structures and methods of forming same |
| CN104091808B (zh) * | 2014-06-25 | 2016-08-17 | 合肥鑫晟光电科技有限公司 | 阵列基板及其制作方法和显示装置 |
| US9505609B2 (en) * | 2015-04-29 | 2016-11-29 | Invensense, Inc. | CMOS-MEMS integrated device with selective bond pad protection |
| US9935047B2 (en) | 2015-10-16 | 2018-04-03 | Taiwan Semiconductor Manufacturing Company, Ltd. | Bonding structures and methods forming the same |
| US10658318B2 (en) * | 2016-11-29 | 2020-05-19 | Taiwan Semiconductor Manufacturing Co., Ltd. | Film scheme for bumping |
| KR101902566B1 (ko) | 2017-07-25 | 2018-09-28 | 엘지디스플레이 주식회사 | 발광 표시 장치 및 이의 제조 방법 |
| US11694967B2 (en) * | 2019-03-14 | 2023-07-04 | Taiwan Semiconductor Manufacturing Company, Ltd. | Package structure and method of fabricating the same |
| CN114093842A (zh) * | 2020-12-23 | 2022-02-25 | 矽磐微电子(重庆)有限公司 | 裸片及其制作方法、芯片封装结构及其制作方法 |
| US20230317648A1 (en) * | 2022-03-04 | 2023-10-05 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor Devices and Methods of Manufacture |
| US20240145258A1 (en) * | 2022-10-27 | 2024-05-02 | Stmicroelectronics Pte Ltd | Panel level semiconductor package and method of manufacturing the same |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6392300B1 (en) * | 1999-06-28 | 2002-05-21 | Kabushiki Kaisha Toshiba | Semiconductor device having an alignment mark formed on the uppermost layer of a multilayer wire |
Family Cites Families (16)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH03105937A (ja) * | 1989-09-19 | 1991-05-02 | Nec Corp | 半導体装置 |
| JPH0488622A (ja) * | 1990-08-01 | 1992-03-23 | Fujitsu Ltd | 半導体装置の製造方法 |
| JPH0590325A (ja) * | 1991-09-27 | 1993-04-09 | Toshiba Corp | 半導体装置のボンデイングパツド |
| KR100258719B1 (ko) | 1993-04-16 | 2000-06-15 | 손욱 | 칩온 글래스용 패널구조 |
| KR960008978A (ko) * | 1994-08-02 | 1996-03-22 | 김주용 | 반도체 소자의 정렬 마크 보호방법 |
| JP3256391B2 (ja) * | 1994-11-28 | 2002-02-12 | キヤノン株式会社 | 回路基板構造 |
| US6875681B1 (en) * | 1997-12-31 | 2005-04-05 | Intel Corporation | Wafer passivation structure and method of fabrication |
| US6586323B1 (en) * | 2000-09-18 | 2003-07-01 | Taiwan Semiconductor Manufacturing Company | Method for dual-layer polyimide processing on bumping technology |
| US6465898B1 (en) * | 2001-07-23 | 2002-10-15 | Texas Instruments Incorporated | Bonding alignment mark for bonds over active circuits |
| JP2004319549A (ja) | 2003-04-11 | 2004-11-11 | Matsushita Electric Ind Co Ltd | 半導体装置およびその製造方法 |
| JP2005012065A (ja) * | 2003-06-20 | 2005-01-13 | Renesas Technology Corp | 半導体装置およびその製造方法 |
| JP2005044971A (ja) | 2003-07-28 | 2005-02-17 | Sharp Corp | 半導体装置及びその製造方法 |
| JP2005109145A (ja) * | 2003-09-30 | 2005-04-21 | Toshiba Corp | 半導体装置 |
| US7122458B2 (en) * | 2004-07-22 | 2006-10-17 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method for fabricating pad redistribution layer |
| KR100577308B1 (ko) * | 2004-12-29 | 2006-05-10 | 동부일렉트로닉스 주식회사 | 반도체 소자 및 그의 제조 방법 |
| KR100712289B1 (ko) * | 2005-04-07 | 2007-04-27 | 삼성에스디아이 주식회사 | 평판표시장치 및 그의 제조방법 |
-
2005
- 2005-11-22 KR KR1020050111994A patent/KR100660893B1/ko not_active Expired - Fee Related
-
2006
- 2006-06-23 US US11/473,852 patent/US7482703B2/en active Active
- 2006-11-20 DE DE102006056066A patent/DE102006056066A1/de not_active Withdrawn
- 2006-11-20 JP JP2006313358A patent/JP2007142436A/ja active Pending
- 2006-11-22 CN CN2006101486633A patent/CN1971903B/zh active Active
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6392300B1 (en) * | 1999-06-28 | 2002-05-21 | Kabushiki Kaisha Toshiba | Semiconductor device having an alignment mark formed on the uppermost layer of a multilayer wire |
Also Published As
| Publication number | Publication date |
|---|---|
| US7482703B2 (en) | 2009-01-27 |
| CN1971903A (zh) | 2007-05-30 |
| KR100660893B1 (ko) | 2006-12-26 |
| DE102006056066A1 (de) | 2007-06-14 |
| JP2007142436A (ja) | 2007-06-07 |
| US20070117343A1 (en) | 2007-05-24 |
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| C06 | Publication | ||
| PB01 | Publication | ||
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| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant |