JP2007142436A - 整列マーク膜を備える半導体素子及びその製造方法 - Google Patents

整列マーク膜を備える半導体素子及びその製造方法 Download PDF

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Publication number
JP2007142436A
JP2007142436A JP2006313358A JP2006313358A JP2007142436A JP 2007142436 A JP2007142436 A JP 2007142436A JP 2006313358 A JP2006313358 A JP 2006313358A JP 2006313358 A JP2006313358 A JP 2006313358A JP 2007142436 A JP2007142436 A JP 2007142436A
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Japan
Prior art keywords
film
alignment mark
pad electrode
passivation
semiconductor device
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Pending
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JP2006313358A
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Japanese (ja)
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JP2007142436A5 (https=
Inventor
Ho-Ik Hwang
皓▲イク▼ 黄
Soo-Cheol Lee
李　受哲
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Samsung Electronics Co Ltd
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Samsung Electronics Co Ltd
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Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Publication of JP2007142436A publication Critical patent/JP2007142436A/ja
Publication of JP2007142436A5 publication Critical patent/JP2007142436A5/ja
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W46/00—Marks applied to devices, e.g. for alignment or identification
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W46/00—Marks applied to devices, e.g. for alignment or identification
    • H10W46/301—Marks applied to devices, e.g. for alignment or identification for alignment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W46/00—Marks applied to devices, e.g. for alignment or identification
    • H10W46/601—Marks applied to devices, e.g. for alignment or identification for use after dicing
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W46/00—Marks applied to devices, e.g. for alignment or identification
    • H10W46/601—Marks applied to devices, e.g. for alignment or identification for use after dicing
    • H10W46/603—Formed on wafers or substrates before dicing and remaining on chips after dicing
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/012—Manufacture or treatment of bump connectors, dummy bumps or thermal bumps
    • H10W72/01251—Changing the shapes of bumps
    • H10W72/01255—Changing the shapes of bumps by using masks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/019—Manufacture or treatment of bond pads
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/072—Connecting or disconnecting of bump connectors
    • H10W72/07221—Aligning
    • H10W72/07223—Active alignment, e.g. using optical alignment using marks or sensors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/072—Connecting or disconnecting of bump connectors
    • H10W72/07231—Techniques
    • H10W72/07236—Soldering or alloying
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/072—Connecting or disconnecting of bump connectors
    • H10W72/07251—Connecting or disconnecting of bump connectors characterised by changes in properties of the bump connectors during connecting
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/241—Dispositions, e.g. layouts
    • H10W72/242—Dispositions, e.g. layouts relative to the surface, e.g. recessed, protruding
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/251—Materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/251—Materials
    • H10W72/252—Materials comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/29—Bond pads specially adapted therefor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/931—Shapes of bond pads
    • H10W72/934—Cross-sectional shape, i.e. in side view
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/941—Dispositions of bond pads
    • H10W72/9415—Dispositions of bond pads relative to the surface, e.g. recessed, protruding
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/975—Substrate or mask aligning feature

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
JP2006313358A 2005-11-22 2006-11-20 整列マーク膜を備える半導体素子及びその製造方法 Pending JP2007142436A (ja)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020050111994A KR100660893B1 (ko) 2005-11-22 2005-11-22 정렬 마크막을 구비하는 반도체 소자 및 그 제조 방법

Publications (2)

Publication Number Publication Date
JP2007142436A true JP2007142436A (ja) 2007-06-07
JP2007142436A5 JP2007142436A5 (https=) 2010-01-14

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JP2006313358A Pending JP2007142436A (ja) 2005-11-22 2006-11-20 整列マーク膜を備える半導体素子及びその製造方法

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Country Link
US (1) US7482703B2 (https=)
JP (1) JP2007142436A (https=)
KR (1) KR100660893B1 (https=)
CN (1) CN1971903B (https=)
DE (1) DE102006056066A1 (https=)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010225934A (ja) * 2009-03-24 2010-10-07 Mitsumi Electric Co Ltd ウエハの製造方法
CN102157497A (zh) * 2011-01-26 2011-08-17 上海宏力半导体制造有限公司 多层堆栈的半导体器件的结构及形成方法
US8274166B2 (en) 2008-07-09 2012-09-25 Renesas Electronics Corporation Semiconductor device and method of manufacturing the same
KR101345393B1 (ko) 2011-03-16 2013-12-24 글로벌파운드리즈 드레스덴 모듈 원 리미티드 라이어빌리티 컴퍼니 & 씨오. 케이지 추가적인 보호 층의 제공을 통한 운송중 반도체 디바이스의 반응성 금속 표면의 보호

Families Citing this family (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8492263B2 (en) 2007-11-16 2013-07-23 Taiwan Semiconductor Manufacturing Company, Ltd. Protected solder ball joints in wafer level chip-scale packaging
US20090174069A1 (en) * 2008-01-04 2009-07-09 National Semiconductor Corporation I/o pad structure for enhancing solder joint reliability in integrated circuit devices
KR20090095076A (ko) * 2008-03-04 2009-09-09 삼성전자주식회사 반도체 집적 회로 장치 및 그 제조 방법
CN101789391B (zh) * 2009-01-23 2012-08-22 中芯国际集成电路制造(上海)有限公司 半导体装置及其制造方法
US8299616B2 (en) * 2010-01-29 2012-10-30 Taiwan Semiconductor Manufacturing Company, Ltd. T-shaped post for semiconductor devices
US8803319B2 (en) 2010-02-11 2014-08-12 Taiwan Semiconductor Manufacturing Company, Ltd. Pillar structure having a non-planar surface for semiconductor devices
US8318596B2 (en) * 2010-02-11 2012-11-27 Taiwan Semiconductor Manufacturing Company, Ltd. Pillar structure having a non-planar surface for semiconductor devices
JP2013004572A (ja) * 2011-06-13 2013-01-07 Mitsubishi Electric Corp 半導体装置の製造方法
US9230932B2 (en) 2012-02-09 2016-01-05 Taiwan Semiconductor Manufacturing Company, Ltd. Interconnect crack arrestor structure and methods
US9515036B2 (en) 2012-04-20 2016-12-06 Taiwan Semiconductor Manufacturing Company, Ltd. Methods and apparatus for solder connections
CN103682085B (zh) * 2012-09-20 2016-08-03 中芯国际集成电路制造(上海)有限公司 一种磁随机存取存储器及其制造方法
CN103199084B (zh) * 2013-03-08 2015-10-14 京东方科技集团股份有限公司 基板对位标记、基板及基板对位标记的制作方法
US8987922B2 (en) 2013-03-11 2015-03-24 Taiwan Semiconductor Manufacturing Company, Ltd. Methods and apparatus for wafer level packaging
US9355979B2 (en) 2013-08-16 2016-05-31 Taiwan Semiconductor Manufacturing Company, Ltd. Alignment structures and methods of forming same
CN104091808B (zh) * 2014-06-25 2016-08-17 合肥鑫晟光电科技有限公司 阵列基板及其制作方法和显示装置
US9505609B2 (en) * 2015-04-29 2016-11-29 Invensense, Inc. CMOS-MEMS integrated device with selective bond pad protection
US9935047B2 (en) 2015-10-16 2018-04-03 Taiwan Semiconductor Manufacturing Company, Ltd. Bonding structures and methods forming the same
US10658318B2 (en) * 2016-11-29 2020-05-19 Taiwan Semiconductor Manufacturing Co., Ltd. Film scheme for bumping
KR101902566B1 (ko) 2017-07-25 2018-09-28 엘지디스플레이 주식회사 발광 표시 장치 및 이의 제조 방법
US11694967B2 (en) * 2019-03-14 2023-07-04 Taiwan Semiconductor Manufacturing Company, Ltd. Package structure and method of fabricating the same
CN114093842A (zh) * 2020-12-23 2022-02-25 矽磐微电子(重庆)有限公司 裸片及其制作方法、芯片封装结构及其制作方法
US20230317648A1 (en) * 2022-03-04 2023-10-05 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor Devices and Methods of Manufacture
US20240145258A1 (en) * 2022-10-27 2024-05-02 Stmicroelectronics Pte Ltd Panel level semiconductor package and method of manufacturing the same

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03105937A (ja) * 1989-09-19 1991-05-02 Nec Corp 半導体装置
JPH0590325A (ja) * 1991-09-27 1993-04-09 Toshiba Corp 半導体装置のボンデイングパツド
JPH08152646A (ja) * 1994-11-28 1996-06-11 Canon Inc 回路基板構造及び該回路基板構造を製造するための位置合せ装置
JP2002500440A (ja) * 1997-12-31 2002-01-08 インテル・コーポレーション ウエハ・パッシベーション構造および製造方法
JP2004319549A (ja) * 2003-04-11 2004-11-11 Matsushita Electric Ind Co Ltd 半導体装置およびその製造方法
JP2005044971A (ja) * 2003-07-28 2005-02-17 Sharp Corp 半導体装置及びその製造方法
JP2005109145A (ja) * 2003-09-30 2005-04-21 Toshiba Corp 半導体装置

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0488622A (ja) * 1990-08-01 1992-03-23 Fujitsu Ltd 半導体装置の製造方法
KR100258719B1 (ko) 1993-04-16 2000-06-15 손욱 칩온 글래스용 패널구조
KR960008978A (ko) * 1994-08-02 1996-03-22 김주용 반도체 소자의 정렬 마크 보호방법
JP4037561B2 (ja) * 1999-06-28 2008-01-23 株式会社東芝 半導体装置の製造方法
US6586323B1 (en) * 2000-09-18 2003-07-01 Taiwan Semiconductor Manufacturing Company Method for dual-layer polyimide processing on bumping technology
US6465898B1 (en) * 2001-07-23 2002-10-15 Texas Instruments Incorporated Bonding alignment mark for bonds over active circuits
JP2005012065A (ja) * 2003-06-20 2005-01-13 Renesas Technology Corp 半導体装置およびその製造方法
US7122458B2 (en) * 2004-07-22 2006-10-17 Taiwan Semiconductor Manufacturing Co., Ltd. Method for fabricating pad redistribution layer
KR100577308B1 (ko) * 2004-12-29 2006-05-10 동부일렉트로닉스 주식회사 반도체 소자 및 그의 제조 방법
KR100712289B1 (ko) * 2005-04-07 2007-04-27 삼성에스디아이 주식회사 평판표시장치 및 그의 제조방법

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03105937A (ja) * 1989-09-19 1991-05-02 Nec Corp 半導体装置
JPH0590325A (ja) * 1991-09-27 1993-04-09 Toshiba Corp 半導体装置のボンデイングパツド
JPH08152646A (ja) * 1994-11-28 1996-06-11 Canon Inc 回路基板構造及び該回路基板構造を製造するための位置合せ装置
JP2002500440A (ja) * 1997-12-31 2002-01-08 インテル・コーポレーション ウエハ・パッシベーション構造および製造方法
JP2004319549A (ja) * 2003-04-11 2004-11-11 Matsushita Electric Ind Co Ltd 半導体装置およびその製造方法
JP2005044971A (ja) * 2003-07-28 2005-02-17 Sharp Corp 半導体装置及びその製造方法
JP2005109145A (ja) * 2003-09-30 2005-04-21 Toshiba Corp 半導体装置

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8274166B2 (en) 2008-07-09 2012-09-25 Renesas Electronics Corporation Semiconductor device and method of manufacturing the same
JP2010225934A (ja) * 2009-03-24 2010-10-07 Mitsumi Electric Co Ltd ウエハの製造方法
CN102157497A (zh) * 2011-01-26 2011-08-17 上海宏力半导体制造有限公司 多层堆栈的半导体器件的结构及形成方法
CN102157497B (zh) * 2011-01-26 2016-03-09 上海华虹宏力半导体制造有限公司 多层堆栈的半导体器件的结构及形成方法
KR101345393B1 (ko) 2011-03-16 2013-12-24 글로벌파운드리즈 드레스덴 모듈 원 리미티드 라이어빌리티 컴퍼니 & 씨오. 케이지 추가적인 보호 층의 제공을 통한 운송중 반도체 디바이스의 반응성 금속 표면의 보호

Also Published As

Publication number Publication date
US7482703B2 (en) 2009-01-27
CN1971903A (zh) 2007-05-30
KR100660893B1 (ko) 2006-12-26
DE102006056066A1 (de) 2007-06-14
CN1971903B (zh) 2010-05-19
US20070117343A1 (en) 2007-05-24

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