CN1937176A - 制作低阻半导体接触的方法及其结构 - Google Patents

制作低阻半导体接触的方法及其结构 Download PDF

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CN1937176A
CN1937176A CNA2006101539202A CN200610153920A CN1937176A CN 1937176 A CN1937176 A CN 1937176A CN A2006101539202 A CNA2006101539202 A CN A2006101539202A CN 200610153920 A CN200610153920 A CN 200610153920A CN 1937176 A CN1937176 A CN 1937176A
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doped region
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CN100565810C (zh
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戈登·M·格里瓦纳
普拉萨德·文卡塔拉曼
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Semiconductor Components Industries LLC
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Abstract

在一种实施方式中，在两种相反掺杂的相邻半导体区上制作硅化物层。制作与两个硅化物都电接触的导体材料。

Description

制作低阻半导体接触的方法及其结构
技术领域
本发明一般涉及到电子学，更确切地说是涉及到制作半导体器件与结构的方法。
背景技术
以前，半导体工业利用各种方法和结构来制作纵向的金属-氧化物-半导体(MOS)晶体管。这些纵向的晶体管一般是利用半导体衬底的掺杂区来制作晶体管的源极接触区，并在源极接触区内制作晶体管的本体区。通常制作的源电极与源区和本体接触区二者电接触。这样的一种纵向晶体管的实例公开在1990年10月2日公布的4,960,723号美国专利中，这里引用作为参考。从源电极至源区和本体区的电阻常会影响晶体管的性能。电阻愈大，则性能愈差。一种执行方案是通过源区制作开孔以露出部分本体接触区，在源区和本体接触区上制作金属层而作为源电极。经常，会在源区或本体接触区出现高阻。
因此，希望有一种方法和结构来对晶体管的源区和本体区提供低阻的电流通道和低接触电阻，并对两个相邻的不同掺杂区提供低阻接触。
发明内容
根据本发明的一方面，提供一种制作半导体接触的方法，包括：提供具有第一表面的半导体衬底；在半导体衬底内制作第一种导电类型的第一掺杂区；在第一表面上毗邻第一掺杂区制作第二种导电类型的第二掺杂区；在第一表面上制作与第二掺杂区电接触的第一硅化物；在部分第一掺杂区上制作第二硅化物；以及制作与第一硅化物和第二硅化物电接触的导体材料。
根据本发明的另一方面，提供一种制作半导体接触的方法，包括：提供半导体衬底，该半导体衬底具有第一种导电类型的第一掺杂区及与第一掺杂区相邻的第二种导电类型的第二掺杂区；制作与部分第一掺杂区接触的第一金属硅化物和与第二掺杂区电接触的第二金属硅化物，其中第一金属与第二金属不同；以及制作与第一金属硅化物和第二金属硅化物电接触的导体。
根据本发明的再一方面，提供一种半导体接触，包括：具有表面的半导体衬底；第一种导电类型的第一掺杂区，该第一掺杂区向半导体衬底中深入第一距离；在半导体衬底表面上的第二掺杂区，该第二掺杂区向半导体衬底中深入第二距离，其中第二掺杂区的第一部分与第一掺杂区的第一部分重叠；与第一掺杂区电接触的第一硅化物；与第二掺杂区电接触的第二硅化物；以及与第一硅化物和第二硅化物电接触的导体材料。
附图说明
图1为本发明部分半导体器件示例实施方式的放大剖面部分；
图2为图1半导体器件的放大剖面部分，表明本发明图1的半导体器件制作方法的实施方式一个阶段的剖面；
图3-图5为图1半导体器件的放大剖面部分，表明本发明图1半导体器件制作方法的实施方式随后各个阶段的剖面；以及
图6为本发明另一种半导体器件一部分的示例实施方式的放大剖面图。
为了说明得简洁明快，图中诸元素不必按比例画图，在不同的图中同样的参考数字代表同样的元素。此外，为简化描述，省略了熟知步骤和元素的描述和细节。这里所用的载流电极意为一种器件元素，例如MOS晶体管的源极或漏极，或双极晶体管的发射极或收集极，或是二极管的阴极或阳极，而控制电极意为一种控制流过器件的电流的器件元素，例如MOS晶体管的栅极，或双极晶体管的基极。虽然这里说明的器件为某种N沟道或P沟道器件，本领域的技术熟练人员将会理解，本发明也可用于互补型器件。为使附图清楚，器件结构的掺杂区边缘一般都为直线和准确的矩形拐角。然而，技术熟练人员都知道，由于掺杂剂的扩散和激活，掺杂区的边缘一般不是直线，拐角也不是准确的角度。
具体实施方式
图1为半导体器件10一部分的示例实施方式的放大剖面部分，半导体器件10包含半导体接触和电极系统18。半导体接触系统18按照一般的方式由箭头来标出。对于图1说明的器件10的示例实施方式，器件10为多元纵向晶体管，包括多个制作在半导体衬底11上的晶体管元，如晶体管17。晶体管17按照一般的方式也由箭头来标出。晶体管17为多个晶体管元的一部分，各晶体管元互连而形成较大的纵向晶体管，例如纵向功率晶体管。本领域的技术熟练人员都知道，纵向功率晶体管含有多个纵向晶体管元。晶体管17包含其栅极结构19。栅极结构19包含导电屏蔽层29，使与衬底13的耦合电容减至最小。屏蔽层29降低了晶体管17的栅-漏电容。这样的导电屏蔽层是本领域的技术熟练人员所熟知的。后面还会看到，接触和电极系统18构成了晶体管17本体区与源区的可靠低阻电连接。在图1所示的示例实施方式中，晶体管17由封闭的几何图形如圆形、六边形或其他封闭的几何图形来构成。例如，若晶体管17为圆形，则结构19的平面图可呈圆环状。晶体管17也典型地包含漏电极15，该电极在衬底11的第二表面上。
图2为器件10一部分的放大剖面图，说明器件10制作方法实施方式一个阶段的一些部分。此描述参见图1和图2。在图2所说明的阶段，晶体管17有源部分的大部分都已在前面制作了。衬底11典型地包含本体半导体衬底12，在其一个表面上制作有外延层13。衬底11有一上表面或顶面14，在其上制作有晶体管17的一些部分。在某些实施方式中，可省去外延层13，本体衬底12的上表面就作为表面14。在表面14上一般有氧化层21，以在半导体工艺操作期间保护衬底11。在图2所示阶段之前，对衬底11的表面14的一部分进行掺杂而形成掺杂区24，这有助于提高器件10的的击穿电压。区域24的掺杂类型通常与层13相反。表面14的一部分被掺杂而形成从表面14向衬底11中扩展的漂移区26。区域26将作为晶体管17的漂移区。工艺上熟知，区域26典型地与区域24重叠，在某些实施方式中，区域26是与区域24分开的。对区域26的一部分进行掺杂而成为向衬底11中伸展第一距离的第一掺杂区36。区域36后来将成为晶体管17的本体接触区。典型地，区域36的掺杂类型与区域26相同，但掺杂浓度较高。再制作第二掺杂区37，该区从表面14向衬底11内伸展第二距离，且至少与区域36的一部分重叠。在其他实施方式中，区域37可邻近于区域36并与之电接触。区域37后来将成为晶体管17的源接触区。制作掺杂区38，该区从表面14延伸至区域26中，并与区域37重叠。区域38的一部分至少典型地扩展至区域37以外，使得区域38的一部分与区域26电接触。区域38的这一部分就成为晶体管17的有源源区。在其他实施方式中，可不用区域37。在区域38与区域26边缘之间的那部分区域26则作为晶体管17的沟道区39。
随后，制作栅结构19，该结构叠置在一部分相应的区域38上和沟道区39上。栅极结构19的一部分制作在沟道区39上，作为晶体管17的栅电极或栅28。栅绝缘层22存留在栅28下面的表面14上，并覆盖沟道区39的一部分。沿栅28的侧壁可制作二氧化硅隔层或氧化物层41。在制作区域38或区域37期间通常使用隔层41，以有助于区域37和38的自对准。隔层41也有助于在后面的工艺操作中在区域37上制作硅化物时隔离栅28。毗邻隔层41可制作氮化硅或氮化物隔层42。在前面的工艺操作期间典型地使用隔层42，以有助于制作区域37和36。与隔层41和42一起来制作区域26、36、37和38的工艺是本领域的技术人员所熟知的。例如，区域26、36和38可用隔层掩蔽或自对准和离子注入来制作，而隔层41和42可用分别制作氧化物和氮化物层，接着进行各向异性腐蚀来制作。
图3为器件10一部分的放大剖面图，说明器件10和晶体管17制作方法实施方式的下一阶段。在高温退火后，掺杂剂已被激活，在栅结构19露出的表面上制作硅化物层45，在区域37上制作第一硅化物层或第一硅化物46。第一硅化物46是由与区域37形成低阻电连接的金属制成的。在此优选的实施方式中，区域37为N型掺杂，硅化物46为硅化钛。硅化物46被用来对区域38提供局部互连。隔层42保证使硅化物46不宽于区域37。此后，制作栅结构19的介电层47，如二氧化硅，以覆盖层45、隔层42，且典型地在层46上伸展第一距离。在某些实施方式中，层47可不在层46上延伸。
然后在层46上制作保护隔层48，以形成至少与区域36的一部分重叠的开孔。隔层48可用各种方法来制作，这都是本领域的技术人员所熟知的。例如，在层46和47上可制作氮化硅层，再用各向异性腐蚀来除去硅化物46上的部分氮化硅层而在层46的一部分上留下隔层48。隔层48形成与部分区域36重叠的一开孔，低阻电接触将制作在这部分区域36处。
图4为器件10一部分的放大剖面图，说明器件10和晶体管17制作方法实施方式的下一阶段。制作通过硅化物46、区域37的开孔，露出区域36的一部分。典型地，制作的开孔深入至区域36中而在其中形成凹部。此开孔通过区域37而露出其侧壁，这可由隔层48或单独的光致抗蚀剂掩模层来确定。
图5为器件10一部分的放大剖面图，说明器件10和晶体管17制作方法实施方式的另一下一阶段。在区域36露出的部分上制作第二硅化物层或第二硅化物51。因为区域36与区域37有不同的掺杂类型，很难制作一种硅化物与区域36和区域37都形成低阻连接。然而，可沿区域37露出的侧壁制作一部分硅化物51。硅化物51是由与区域36的材料形成低阻电连接的金属制成的。在优选的实施方式中，区域36为P型掺杂，硅化物51为硅化铂，然而，也可用其他金属来制作不同类型的硅化物而与区域36形成低阻连接。虽然在区域37侧壁上的这部分硅化物51可不与之形成低阻连接，应注意到，在区域37表面上生成的硅化物46与区域37形成低阻连接。接着，除去隔层48。作为选择，隔层48可以保留，如果隔层48是由导电材料如钨(W)或硅化钨(WSi)等制成的话。本领域的技术人员应了解，也可在制作硅化物51前除去隔层48，例如在通过层37开孔而露出区域36后就除去隔层48。在介电层47中与区域36和37重叠的接触孔中制作接触结构。
由硅化物46和51构成的低阻电连接成为晶体管17的源和本体接触结构。硅化物46和51的接触结构形成了与区域37和36台阶区的可靠低阻电连接。硅化物46也提供了与由区域38构成的源区的低阻局部互连通道。这有助于降低晶体管17的源电阻。注意，由于区域38构成的源区与栅28是离开的，源区的横向电阻是个重要参数。因此，硅化物46提供了较低的源电阻，也改进了工艺。由于在制作硅化物后一般不应使用高温处理工艺步骤，对露出的部分区域36一般不可能再作掺杂和退火，因此，使用硅化物51有助于形成低阻连接而不会干扰硅化物46所提供的低阻连接。
本领域的技术人员都知道，单一硅化物或其他金属连接如铝-硅合金可用作硅化物46和51，而不是用两种硅化物46和51。单一硅化物的电阻可不如硅化物46和51所提供者那样低。
回过来再参见图1，制作与硅化物46和51电连接的导体材料52，从而通过硅化物46形成与区域37的低阻电连接，通过硅化物51形成与区域36的低阻电连接。硅化物46和51与材料52制成的电极一起构成了接触结构，此结构起着半导体接触和电极系统18的作用。导体材料52可为半导体工艺所用的任何导电材料，如钛、钨化钛、铝或铝合金。对两个不同掺杂的半导体区使用两种不同的硅化物便于使接触结构与两种掺杂区都形成低阻电连接。在一种示例实施方式中，硅化物46和51的接触结构使电阻降低约一个数量级。
虽然图1所示的示例实施方式说明的是晶体管17所用的硅化物46和51分别与区域37和36所构成的结构，此接触结构也可用于其他类型的半导体器件包括分立的晶体管而非多元晶体管、平面型晶体管、以及需要对不同掺杂类型的两个半导体区有低阻电连接的其他半导体器件。
图6为半导体器件70一部分的示例实施方式放大剖面图，半导体器件70具有电接触结构85，这是图1-图5所描述的电极和接触系统18的一种替代实施方式。半导体器件70通常包含有助于提高器件70击穿电压的掺杂区71。区域71与图1-图5中的区域24相似。器件70通常也包含制作在衬底11中的掺杂区72，它作为晶体管或利用接触结构85的其他半导体器件的漂移区。区域72类似于图1-图5中的区域26。在某些实施方式中可省去区域71和72。器件70还包含第一掺杂区73和第二掺杂区74，二者与图1-图5中的区域36和37一样具有相反的掺杂类型。区域73是在衬底11的第一部分进行掺杂而在衬底11中深入第一距离而形成，区域74是在衬底11的第二部分进行掺杂而在衬底11中深入第二距离而形成，但其导电类型与区域73相反。典型地，区域73在衬底11中比区域74深入得更多。区域74和73彼此相邻，优选地，区域73和74有一部分互相重叠。重叠的部分由虚线表示。至少在区域73的一部分上制作第一硅化物层或第一硅化物77。在此优选实施方式中，硅化物77类似于图1-图5中的硅化物46。至少在区域74的一部分上制作第二硅化物78。在此优选实施方式中，硅化物78类似于图1-图5中的硅化物51。在衬底11上制作介电层79，对之刻图形开孔而露出硅化物77和78。在硅化物77和78上制作导体材料80而与之形成电连接。导体80与图1-图5中的导体52类似。在其他实施方式中，区域74可向区域73中延伸某一距离，因此，硅化物78可伸展而覆盖区域74。在其他实施方式中，在分别制作硅化物77和78之前，可在区域73或74中制作凹部。
考虑到上述全部，显然公开了一种新的器件和方法。这包括，与其他特点一起，对半导体结构制作低电阻的接触结构，这种半导体结构的两个相反掺杂的半导体区具有共同的电连接。这种低电阻连接便于使此种接触结构对半导体结构的各个部分提供局部互连。对第一区制作第一硅化物，对第二区制作第二硅化物，就可对每一层制作硅化物，从而实现对各个掺杂区的低阻电连接。
虽然以具体的优选实施方式描述了本发明的主旨，显然熟悉半导体工艺的技术人员可对之作出许多选择和变动。一般的技术人员会知道，所说明的步骤只是一种示例，且只是在半导体衬底11上制作器件10所需的部分制作工艺步骤。确定类似的隔层，例如隔层48，也可使用体接触结构来将体接触的尺寸减小至某些光刻设备的限度内。这种阶梯式的接触也可改善金属化在小的接触孔中的阶梯覆盖而不需要钨栓塞或其他填充技术。另一种实施方式是对于局部互连硅化物的，是用第二种类似的硅化物来制作本体接触，从而对两种掺杂区提供局部互连和自对准接触。本领域的技术人员也会了解，此种接触结构也可用于沟槽型晶体管以及在所说明的晶体管10实施方式中的平面型结构。沟槽型晶体管典型地有一沟槽，此沟槽从表面14，经过区域38和26而延伸至区域13中。栅电极会被制作在沟槽内，使当晶体管开通时在沟槽的侧壁上形成沟道。例如，一种沟槽型晶体管可省去区域37，且由区域38构成的源区伸展至硅化物46下面。在这样一种结构中，一部分硅化物51可在延伸的区域38侧壁上，而硅化物51的第二部分可成为对本体区36的接触。在某些实施方式中，单一硅化物可用于接触区38和36，而无需两种硅化物。

Claims (10)

1.一种制作半导体接触的方法，包括：
提供具有第一表面的半导体衬底；
在半导体衬底内制作第一种导电类型的第一掺杂区；
在第一表面上毗邻第一掺杂区制作第二种导电类型的第二掺杂区；
在第一表面上制作与第二掺杂区电接触的第一硅化物；
在部分第一掺杂区上制作第二硅化物；以及
制作与第一硅化物和第二硅化物电接触的导体材料。
2.权利要求1的方法，其中制作第二掺杂区包括制作覆盖所述部分第一掺杂区的第二掺杂区；
其中在所述部分第一掺杂区上制作第二硅化物包括穿过第二掺杂区制作开孔而露出所述部分第一掺杂区；及
其中穿过第二掺杂区制作开孔包括制作与第二掺杂区电接触的第一硅化物，制作覆盖第一硅化物的保护隔层并露出覆盖所述部分第一掺杂区的部分第二掺杂区，并穿过所述部分第二掺杂区制作开孔而露出所述部分第一掺杂区。
3.权利要求1的方法，还包括经同一接触孔制作第一硅化物和第二硅化物。
4.权利要求1的方法，其中在所述部分第一掺杂区上制作第二硅化物包括在邻近第二掺杂区的第一掺杂区中制作凹部，再沿凹部制作第二硅化物。
5.权利要求1的方法，其中制作第二硅化物包括对第一硅化物使用第一金属，对第二硅化物使用不同的金属。
6.一种制作半导体接触的方法，包括：
提供半导体衬底，该半导体衬底具有第一种导电类型的第一掺杂区及与第一掺杂区相邻的第二种导电类型的第二掺杂区；
制作与部分第一掺杂区接触的第一金属硅化物和与第二掺杂区电接触的第二金属硅化物，其中第一金属与第二金属不同；以及
制作与第一金属硅化物和第二金属硅化物电接触的导体。
7.权利要求6的方法，其中提供半导体衬底包括提供所述第一掺杂区，第一掺杂区比第二掺杂区更深入半导体衬底。
8.一种半导体接触，包括：
具有表面的半导体衬底；
第一种导电类型的第一掺杂区，该第一掺杂区向半导体衬底中深入第一距离；
在半导体衬底表面上的第二掺杂区，该第二掺杂区向半导体衬底中深入第二距离，其中第二掺杂区的第一部分与第一掺杂区的第一部分重叠；
与第一掺杂区电接触的第一硅化物；
与第二掺杂区电接触的第二硅化物；以及
与第一硅化物和第二硅化物电接触的导体材料。
9.权利要求8的半导体接触，其中第一距离大于第二距离，并且其中第二掺杂区与第一掺杂区重叠。
10.权利要求8的半导体接触，其中第二硅化物在表面上，并且还包含穿过第二掺杂区的开孔及在第一掺杂区中制作凹部，其中第一硅化物在部分凹部上。
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CN104810289A (zh) * 2014-01-27 2015-07-29 北大方正集团有限公司 一种vdmos管的制造方法和vdmos
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