CN1933137A - 半导体装置 - Google Patents

半导体装置 Download PDF

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CN1933137A
CN1933137A CNA200610129132XA CN200610129132A CN1933137A CN 1933137 A CN1933137 A CN 1933137A CN A200610129132X A CNA200610129132X A CN A200610129132XA CN 200610129132 A CN200610129132 A CN 200610129132A CN 1933137 A CN1933137 A CN 1933137A
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electrode
semiconductor device
semiconductor chip
straight line
integrated circuit
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CN100521174C (zh
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桥元伸晃
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Seiko Epson Corp
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Seiko Epson Corp
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Abstract

本发明的目的在于提供一种能够高密度配置电极、且能够利用集成电路的设计上的制约少的半导体芯片的半导体装置。半导体装置包括：半导体芯片(10)，其形成有集成电路(12)；电极(14)，其形成在半导体芯片(10)的第一区域，排列成多行多列；树脂突起(20)，其形成在半导体芯片(10)的包围第一区域的第二区域内；和多个电连接部(30)，其形成在树脂突起(20)上，与多个电极(14)电连接。

Description

半导体装置
技术领域
本发明涉及一种半导体装置。
背景技术
为了实现电子部件的小型化，半导体装置的外形优选小型化。但是，随着半导体装置作用的多样化，形成于半导体芯片的集成电路的高集成化逐步发展。即，目前，正在开发能够同时满足半导体装置的小型化和集成电路的高集成化这两方面要求的半导体装置。
为了满足该要求，正在关注一种外形与半导体芯片大致相同大小的半导体装置(参照特开平2-272737号公报)。如果基于该类型的半导体装置能够使半导体芯片小型化，则能够实现半导体装置的小型化。
可是，为了确保半导体装置的可靠性，需要集成电路以各种制约为基础进行设计。如果减少集成电路设计上的制约，则能够减小集成电路区域，由此能够减小半导体芯片。即，如果能够利用集成电路设计上的制约少的半导体芯片，则能够制造外形小的半导体装置。
发明内容
本发明的目的在于提供一种能够实现小型化、且可靠性高的半导体装置。
(1)本发明的半导体装置包括：半导体芯片，其形成有集成电路；
电极，其形成在所述半导体芯片的第一区域，排列成多行多列；
树脂突起，其形成在所述半导体芯片的包围所述第一区域的第二区域内；和
多个电连接部，其形成在所述树脂突起上，与所述多个电极电连接。
根据本发明，可提供能够实现小型化、且可靠性高的半导体装置。
(2)在该半导体装置中，
所述电极包括排列成多行多列的一组电极，
所述一组电极分别配置在平行延伸的多条第一直线和与所述第一直线交叉的多条第二直线的任意一个交点上，
与所述一组电极电连接的所述电连接部形成在所述树脂突起上，所述树脂突起形成为沿着所述第一直线延伸的形状，数量比所述第一直线少。
(3)在该半导体装置中，
与所述一组电极电连接的所述电连接部，全部形成在一个所述树脂突起上。
(4)在该半导体装置中，
所述第一和第二直线可以正交。
(5)在该半导体装置中，
所述第一和第二直线可以斜交叉。
(6)在该半导体装置中，
所述半导体芯片形成为长方形，
所述第一直线可以平行于所述半导体芯片的短边而延伸。
(7)在该半导体装置中，
所述半导体芯片形成为长方形，
所述第一直线可以平行于所述半导体芯片的长边而延伸。
(8)在该半导体装置中，
所述多个电极与多个I/O单元电连接，
在所述半导体芯片上，形成有排列成多行多列的I/O单元，
各个所述电极可以与任意的所述I/O单元电连接。由此，能够减小半导体芯片的集成电路区域。因此，由于可利用外形小的半导体芯片，所以，能够进一步使半导体装置小型化。
(9)在该半导体装置中，
所述一组电极可以分别形成在对应的任意一个所述I/O单元上。由此，可提供能够进一步小型化的半导体装置。
(10)在该半导体装置中，
所述电极可以形成为与所述集成电路的至少一部分重复。
附图说明
图1是用于对应用了本发明的实施方式的半导体装置进行说明的图；
图2是用于对应用了本发明的实施方式的半导体装置进行说明的图；
图3是用于对应用了本发明的实施方式的半导体装置进行说明的图；
图4是用于对应用了本发明的实施方式的半导体装置进行说明的图；
图5是用于对应用了本发明的实施方式的半导体装置进行说明的图；
图6是用于对应用了本发明的实施方式的变形例的半导体装置进行说明的图。
图中：1—半导体装置；10—半导体芯片；12—集成电路；14—电极；16—钝化膜；18—电极；19—电极；20—树脂突起；21—树脂突起；30—电连接部；32—布线；34—电连接部；40—布线基板；42—电连接部；50—粘结剂；60—电极；101—第一直线；102—第二直线；103—第一直线；104—第二直线。
具体实施方式
下面，参照附图，对应用了本发明的实施方式进行说明。但是，本发明并不限定于下面的实施方式。另外，本发明包括将下面所示的内容进行自由组合的实施方式。
下面，参照图1～图3，对应用了本发明的实施方式的半导体装置进行说明。在此，图1是应用了本发明的实施方式的半导体装置1的概略图。另外，图2是图1的局部放大图。并且，图3是图2的III-III线剖面的局部放大图。
如图1～图3所示，本实施方式的半导体装置包括半导体芯片10。半导体芯片10例如可以是硅基板。可以在半导体芯片10上形成集成电路12(参照图3)。集成电路12的结构并无特别的限定，例如，可以包括晶体管等有源元件，或电阻、线圈、电容等无源元件。半导体芯片10的形成有集成电路12的面(有源面)可以形成为长方形(参照图1)。但是，半导体芯片10的有源面也可以形成为正方形(未图示)。再有，本发明也可以扩张到含有多个半导体芯片的半导体晶片(未图示)。此时，半导体晶片可以包括成为多个半导体芯片的区域。
如图1～图3所示，本实施方式的半导体装置包括形成在半导体芯片10上的多个电极14。电极14排列成多行多列。电极14形成在半导体芯片10的第一区域内。相反，也可以指定半导体芯片的形成有电极14的区域作为第一区域。电极14也可以形成于半导体芯片10的形成有集成电路12的面(有源面)。电极14可以形成为与集成电路12的至少一部分重复。此时，集成电路12可以形成为与第一区域的至少一部分重复。电极14例如可以形成为与构成集成电路12的晶体管重复。电极14可以和集成电路12电连接。或者，也可以包括未与集成电路12电连接的导电体而称为电极14。电极14可以是半导体芯片的内部布线的一部分。电极14可以由铝或铜等金属形成。可以在半导体芯片10上形成钝化膜16，此时，电极14可以是从钝化膜16露出的露出区域(参照图3)。再有，钝化膜例如可以是SiO2或SiN等的无机绝缘膜。或者，钝化膜16也可以是聚酰亚胺树脂等的有机绝缘膜。
如图1和图2所示，电极14可以包括排列成多行多列的一组电极18。电极18可以配置在分别平行延伸的多条第一直线101和与第一直线101交叉的多条第二直线102的任意一个交点上。如图1和图2所示，一组电极18可以配置在两根第一直线101上。但是，一组电极18也可以配置在大于等于三根的多条第一直线101上(未图示)。在半导体芯片10(半导体芯片10的有源面)形成为长方形的情况下，第一直线101可以是平行于该长方形的短边而延伸的直线。或者，第一直线101也可以是平行于半导体芯片10的长边而延伸的直线。另外，第二直线102可以是与第一直线101正交的直线。或者，第二直线102也可以是与第一直线101斜交叉的直线。例如，如图1和图2所示，电极18可以排列成4×2。但是，本实施方式的半导体装置并不限定于此，电极18也可以排列成M×N(但是，M和N是大于等于2的整数)。
电极14还可以包括其他组的电极19，该电极19沿着与第一直线101交叉的方向延伸的直线排列。在半导体芯片10(半导体芯片10的有源面)形成为长方形的情况下，电极19可以沿着该长方形的长边排列。如图1所示，电极19也可以沿着该长边排列成一列。但是，电极19也可以沿着该长边排列成多列。即，电极19可以排列成多行多列。
可以在半导体芯片10上形成排列成多行多列的I/O单元。并且，电极14可以与I/O单元电连接。与一组电极18电连接的I/O单元可以排列成多行多列。此时，电极18可以分别形成在对应的I/O单元上。另外，电极19也可以分别形成在对应的I/O单元上。此时，电极14可以全部形成在对应的I/O单元上。
如图1所示，本实施方式的半导体装置包括形成在半导体芯片10上的多个树脂突起20。树脂突起20形成在半导体芯片10的形成有电极14的面(有源面)上。树脂突起20也可以形成在钝化膜16上。并且，树脂突起20形成在包围第一区域的第二区域内。即，树脂突起20可以(仅)形成在比形成有电极14的区域靠向外侧的区域。树脂突起20还可以(仅)形成为比形成有集成电路12的区域靠向外侧。但是，本实施方式的半导体装置还可以包括配置在比树脂突起20(集成电路12)靠向外侧的区域的电极(未图示)。再有，在本发明的半导体装置中，也可以在一个半导体芯片上仅形成一个一体形成的树脂突起。此时，树脂突起可以在第二区域内以包围第一区域的方式形成。
树脂突起20的材料并无特别的限定，可以采用已经公知的任意一种材料。例如，可以由聚酰亚胺树脂、硅改性聚酰亚胺树脂、环氧树脂、硅改性环氧树脂、苯并环丁烯(BCB；benzocyclobutene)、聚苯并恶唑(PBO；polybenzoxazole)、酚醛树脂等树脂形成树脂突起20。另外，树脂突起20的形状并无特别的限定。例如，树脂突起20可以形成为直线状(参照图1)。此时，树脂突起20可以形成为沿着半导体芯片10的边延伸。树脂突起20可以包括形成为平行于第一直线101而延伸的形状的树脂突起21。树脂突起21可以形成为沿着半导体芯片10的短边延伸的形状。另外，树脂突起20的表面可以形成为曲面。此时，如图2所示，树脂突起20的截面形状可以形成为半圆状。但是，树脂突起20也可以形成为半球状(未图示)。
本实施方式的半导体装置包括多个电连接部30。电连接部30形成在树脂突起20上。电连接部30分别与电极14电连接。例如，电连接部30可以指定以从电极14上抽出而到达树脂突起20上的方式形成的布线32的一部分(与树脂突起20重复的区域)。再有，如图1所示，也可以在一个树脂突起20上形成多个电连接部30。但是，也可以在一个树脂突起20上仅形成一个电连接部30(未图示)。
在本实施方式的半导体装置中，与一组电极18电连接的电连接部34，可以形成在比第一直线101的根数少的树脂突起20(树脂突起21)上。此时，树脂突起20可以形成为沿着第一直线101延伸的形状。即，与一组电极18电连接的电连接部34，能够以可划分成沿着第一直线101延伸的、数量比第一直线101少(例如一个)的组的方式进行排列。例如，如图1所示，与一组电极18电连接的电连接部34可以全部形成在一个树脂突起20(树脂突起21)上。
布线32(电连接部30、34)的构造以及材料并无特别的限定。例如，布线32可以形成为单层。或者，布线32也可以形成为多层。此时，布线32可以包括由钨钛形成的第一层、和由金形成的第二层(未图示)。
本实施方式的半导体装置1可以形成以上的结构。图4表示半导体装置1安装于布线基板40的情况。在此，布线基板40可以是刚性基板(例如玻璃基板、硅基板)，也可以是柔性基板(例如薄膜基板)。布线基板40具有电连接部42。电连接部42可以是布线基板40的布线图案的一部分。半导体装置1可以半导体芯片10的有源面与布线基板40对置的方式搭载。并且，布线基板40的电连接部42和电连接部30可以接触而电连接。详细而言，半导体装置1的电连接部30可以与布线基板40的电连接部42接触而电连接。于是，通过树脂突起20的弹力能够按压电连接部30和电连接部42。因此，能够提供电连接可靠性高的半导体装置。并且，半导体装置1可以通过粘结剂50粘结到布线基板40上。半导体装置1还可以通过粘结剂50而固定在布线基板40上。通过利用粘结剂50来确保半导体装置1和布线基板40的间隔，可以维持树脂突起20处于弹性变形的状态。再有，虽然未图示，但是，半导体装置1也可以直接安装到构成电子模块1000的玻璃基板上。此时，电子模块1000的布线图案可以形成在玻璃之上。在电子模块1000的布线图案形成于玻璃之上的情况下，形成为被称作COG(Chip On Glass)安装的安装方式。其连接机理可与上述相同。
并且，图5表示安装了半导体装置1的电子模块1000。电子模块1000可以是显示器件。显示器件例如可以是液晶显示器件或EL(ElectricalLuminescence)显示器件。并且，半导体装置1可以是控制显示器件的驱动IC。
根据本发明，可以提供能够实现小型化、且可靠性高的半导体装置。下面，对其效果进行说明。
以往，半导体芯片(半导体芯片)的电极一般避开有源面的中央区域(与集成电路重复的区域)而形成在周缘区域。作为其理由可以考虑各种各样的情况，例如可举出，防止因安装时的压力而引起集成电路的特性产生变化。详细而言，在安装半导体装置之际、或对半导体芯片进行封装之际，会对电极施加力。在该情况下，如果集成电路配置在电极的正下方，则安装时对集成电路施加力，有可能会使集成电路的特性产生变化。为了防止该情况，需要以不与集成电路重复的方式配置电极。并且，这成为对电极配置的制约，由此成为制约集成电路设计的原因。
但是，如先前所说明那样，根据半导体装置1，电连接部30可作为外部端子而利用。并且，电连接部30形成在树脂突起20上。因此，根据半导体装置1可以不对电极14施加力而安装半导体装置。因此，根据本发明，即使在电极14形成在集成电路12上的情况下，也能够提供安装时集成电路12的特性不会产生变化的半导体装置。即，根据本发明，即使在自由配置电极14的情况下也能够确保集成电路12的可靠性，由此，能够实现电极14的高密度配置。
由此，根据本发明，能够提高半导体芯片10的集成电路12的设计自由度。以往，为了以不和集成电路12重复的方式配置电极，将内部布线牵引到半导体芯片的内部。但是，若半导体装置的微细化或集成电路的高集成化发展，则难以进行内部布线的牵引。并且，因为内部布线不能牵引的原因，可以设想在集成电路12的设计上产生制约。可是，根据半导体装置1，由于电极14的配置的制约减少，所以，能够减少集成电路12的设计上的制约。因此，提高了集成电路12的设计自由度。即，根据半导体装置1，可提供一种能够利用集成电路12的设计自由度高的半导体芯片10的半导体装置。并且，由于集成电路12的设计自由度提高，所以，能够确保集成电路12的可靠性，且能够减小集成电路12的形成区域。另外，根据本发明，通过将电极14排列成多行多列，能够减小电极14的形成区域。因此，根据半导体装置1，可提供外形小、且可靠性高的半导体装置。
另外，通过将I/O单元排列成多行多列，可进一步使半导体芯片10小型化。即，通过将I/O单元排列成多行多列，能够减小I/O单元所占有的面积，同时，还能够节省半导体芯片10的集成电路12的设计空间，所以，能够使半导体芯片10小型化。此外，通过使电极14(电极18)(以与I/O单元的至少一部分重复的方式)形成在I/O单元上，无需在I/O单元形成区域的外侧设置用于形成电极的空间，所以，可进一步实现半导体芯片10的小型化。再有，如先前所说明那样，根据半导体装置1，可以不对电极14施加力地安装半导体装置。因此，即使在电极14形成于I/O单元上的情况下，也能够确保半导体装置的可靠性。
另外，根据半导体装置1，能够提供通用性高的半导体装置。详细而言，根据半导体装置1，即使是电极14的排列(集成电路12的设计)不同的半导体芯片，也能够使电连接部30形成在相同位置。因此，能够将集成电路12的设计不同的半导体芯片安装到一块布线基板上。或者，即使是具有相同设计的集成电路12的半导体芯片10，也能够改变电连接部30的排列。因此，能够将形成有相同集成电路的半导体芯片安装到不同设计的布线基板上。
图6是用于对应用了本发明的实施方式的变形例的半导体装置进行说明的图。但是，在图6中为了简单起见，省略了树脂突起20以及布线32(电连接部30)。在本实施方式的半导体装置中，半导体芯片10的电极60可以全部配置在平行延伸的多条第一直线103与平行延伸的多条第二直线104的交点上。此时，如图6所示，第一及第二直线103、104可以是正交的直线。另外，多条第一及第二直线可以分别以等间隔排列。详细而言，多条第一直线103可以等间隔排列。另外，多条第二直线104也可以等间隔排列。此时，第一直线103与第二直线104可以相同的间隔排列。但是，第一及第二直线也可以是斜交叉的直线(未图示)。根据本实施方式，也能够提供可靠性高、且能够实现小型化的半导体装置。
另外，在应用了本发明的实施方式的其他变形例中，半导体装置也可以形成为具有薄片状半导体基板的结构(未图示)。此时，薄片状半导体基板包括多个成为半导体芯片10的区域。另外，薄片状半导体基板在每个成为半导体芯片10的区域，形成为制作完成了上述任意一种构造的结构。由此，通过将薄片状半导体基板切割成单片，能够提供具有半导体芯片10的、上述任意一种半导体装置。
再有，本发明并不限定于上述的实施方式，可实施各种变形。例如，本发明包括与实施方式所说明的结构实际上相同的结构(例如，功能、方法以及结果相同的结构，或者目的以及效果相同的结构)。另外，本发明还包括对实施方式所说明的结构的非本质部分进行了更换的结构。另外，本发明包括能够与实施方式所说明的结构发挥相同的作用效果，或能够达到相同目的的结构。另外，本发明包括对实施方式所说明的结构附加了公知技术的结构。

Claims (10)

1.一种半导体装置，其中，包括：
半导体芯片，其形成有集成电路；
电极，其形成在所述半导体芯片的第一区域，排列成多行多列；
树脂突起，其形成在所述半导体芯片的包围所述第一区域的第二区域内；和
多个电连接部，其形成在所述树脂突起上，与所述多个电极电连接。
2.根据权利要求1所述的半导体装置，其中，
所述电极包括排列成多行多列的一组电极，
所述一组电极分别配置在平行延伸的多条第一直线和与所述第一直线交叉的多条第二直线的任意一个交点上，
与所述一组电极电连接的所述电连接部形成在所述树脂突起上，所述树脂突起形成为沿着所述第一直线延伸的形状，数量比所述第一直线少。
3.根据权利要求2所述的半导体装置，其中，
与所述一组电极电连接的所述电连接部，全部形成在一个所述树脂突起上。
4.根据权利要求2或3所述的半导体装置，其中，
所述第一和第二直线正交。
5.根据权利要求2或3所述的半导体装置，其中，
所述第一和第二直线斜交叉。
6.根据权利要求2～5中任一项所述的半导体装置，其中，
所述半导体芯片形成为长方形，
所述第一直线平行于所述半导体芯片的短边而延伸。
7.根据权利要求2～5中任一项所述的半导体装置，其中，
所述半导体芯片形成为长方形，
所述第一直线平行于所述半导体芯片的长边而延伸。
8.根据权利要求1～7中任一项所述的半导体装置，其中，
在所述半导体芯片上形成有排列成多行多列的I/O单元，
各个所述电极与任意的所述I/O单元电连接。
9.根据权利要求8所述的半导体装置，其中，
所述一组电极分别形成在对应的任意一个所述I/O单元上。
10.根据权利要求1～9中任一项所述的半导体装置，其中，
所述电极形成为与所述集成电路的至少一部分重复。
CNB200610129132XA 2005-09-13 2006-09-11 半导体装置 Expired - Fee Related CN100521174C (zh)

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