CN1933136A - 半导体装置 - Google Patents

半导体装置 Download PDF

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CN1933136A
CN1933136A CNA200610129069XA CN200610129069A CN1933136A CN 1933136 A CN1933136 A CN 1933136A CN A200610129069X A CNA200610129069X A CN A200610129069XA CN 200610129069 A CN200610129069 A CN 200610129069A CN 1933136 A CN1933136 A CN 1933136A
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semiconductor device
semiconductor chip
electrode
integrated circuit
resin projection
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CN100524714C (zh
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桥元伸晃
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Seiko Epson Corp
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Seiko Epson Corp
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Abstract

本发明提供一种半导体装置，包括形成集成电路(12)的半导体芯片(10)、形成在半导体芯片(10)上且排列为多行多列的电极(14)、在半导体芯片(10)的形成电极(14)的面上形成的多个树脂突起(20)和形成在树脂突起(20)上的多个电连接部(30)。从而可提供小型化且高可靠性的半导体装置。

Description

半导体装置
技术领域
本发明涉及半导体装置。
背景技术
为了将电子部件小型化，优选半导体装置的外形小型化。但是，随着半导体装置的功能的多样化，形成在半导体芯片上的集成电路越来越高集成化。即现在正在能够同时满足开发半导体装置小且集成电路的高集成化的两个要求的半导体装置的开发。
为了满足该要求，外形与半导体芯片大致相同大小的半导体装置越来越受注目(特开平2-272737)。如果根据该类型的半导体装置，能够使半导体芯片小型化，可将半导体装置小型化。
然而，为了确保半导体装置的可靠性，集成电路根据各种制约而设计。如果集成电路的设计的制约变少，则可减小集成电路区域，能够减小半导体芯片。即如果能够利用集成电路的设计的制约减少的半导体芯片，则能够制造外形小的半导体装置。
发明内容
本发明的目的在于，能够提供可小型化且高可靠性的半导体装置。
(1)本发明相关的半导体装置包括：形成集成电路的半导体芯片；形成在所述半导体芯片上且排列为多行多列的电极；在所述半导体芯片的形成所述电极的面上形成的多个树脂突起；和形成在所述树脂突起上且与所述多个电极电连接的多个电连接部。根据本发明，能够提供小型化且高可靠性的半导体装置。
(2)在该半导体装置中，所述电极也可配置于平行延伸的多条第一直线和按照与所述第一直线正交的方式延伸的多条第二直线的各个交点。
(3)在该半导体装置中，所述半导体芯片的外形为矩形，所述第一以及第二直线也可平行于所述半导体芯片的某个边而延伸。
(4)在该半导体装置中，所述树脂突起也可形成为平行于所述半导体芯片的某个边而延伸的形状。
(5)在该半导体装置中，也可在所述半导体芯片的某个边附近形成一个所述树脂突起。
(6)在该半导体装置中，也可沿所述半导体芯片的一条所述边形成多个所述树脂突起。
(7)在该半导体装置中，在所述半导体芯片上形成排列为多行多列的I/O单元，各个所述电极也可与某个所述I/O单元电连接。由此，能够减小半导体芯片的集成电路区域。因此，由于能够利用外形小的半导体芯片，从而能够使半导体装置进一步小型化。
(8)在该半导体装置中，各个所述电极也可按照与所对应的某个所述I/O单元的至少一部分重叠的方式形成。由此，能够提供一种可小型化的半导体装置。
(9)在该半导体装置中，所述电极也可按照与所述集成电路的至少一部分重叠的方式形成。
附图说明
图1是对适用本发明的实施方式相关的半导体装置进行说明的图。
图2是对适用本发明的实施方式相关的半导体装置进行说明的图。
图3是对适用本发明的实施方式相关的半导体装置进行说明的图。
图4是对适用本发明的实施方式相关的半导体装置进行说明的图。
图5是对适用本发明的实施方式相关的半导体装置进行说明的图。
图6是用于对适用本发明的实施方式的变形例相关的半导体装置进行说明的图。
图中：1-半导体装置；10-半导体芯片；12-集成电路；14-电极；15-边；16-钝化膜；18-电极；19-边；20-树脂突起；30-电连接部；32-布线；40-布线基板；42-基底基板；44-电连接部；50-粘接剂；60-电极；101-第一直线；102-第二直线；103-第一直线；104-第二直线；1000-电子组件。
具体实施方式
以下，参照附图对适用本发明的实施方式进行说明。但是，本发明并不由以下的实施方式限定。此外，本发明包括自由组合以下内容的方案。
以下，参照图1～图3，对适用本发明的实施方式相关的半导体装置进行说明。在此，图1为适用本发明的实施方式相关的半导体装置1的概略图。此外，图2是图1的一部分放大图。而且，图3为图2的III-III线剖面的一部分放大图。
本实施方式相关的半导体装置，如图1以及图3所示，包括半导体芯片10。半导体芯片10也可例如为硅基板。半导体芯片10上也可形成集成电路12(参照图3)。集成电路12的结构并不特别限定，但也可包括例如晶体管等的有源元件、电阻、线圈、电容器等的无源元件。半导体芯片10的集成电路12所形成的面(有源面)也可形成长方形(参照图1)。但是，半导体芯片10的有源面也可形成正方形(未图示)。
本实施方式相关的半导体装置，如图1～图3所示，包括多个电极14。电极14排列为多行多列。电极14也可排列为栅格状。电极14如图2所示也可排列在平行延伸的多条第一直线101和按照与第一直线101交叉的方式延伸的多条第二直线102之间的各交点。并且，第一以及第二直线101、102也可正交。第一以及第二直线101、102也可为与半导体芯片10的边平行延伸的直线。例如，如图1以及图2所示，第一直线101也可与半导体芯片10的边15平行。此时，半导体芯片10的边15也可为半导体芯片10的有源面的短边。而且，电极14也可形成在边15的周边区域。另外，电极14例如图1以及图2所示，也可排列为4×2。但是，本实施方式相关的半导体装置并不限于此，电极14也可排列为M×N(其中，M以及N为2以上的整数)。另外，电极14也可随机配置。即电极14也可不具有规则性而自由排列。电极14也可形成于在半导体芯片10的内部形成的集成电路元件之上。
电极14也可形成为与集成电路12(集成电路12的电路元件)的至少一部分重叠。电极14也可与集成电路12(构成集成电路12的电路元件)电连接。电极14也可与形成在半导体芯片10上的I/O单元电连接，此时多个电极14也可形成在分别对应的I/O单元上。另外，I/O单元也可排列为多行多列。
电极14也可为半导体芯片的内部布线(或者电路元件的电极)的一部分。电极14也可由铝或铜等的金属形成。在半导体芯片10上也可形成钝化膜16，此时电极14也可为钝化膜16的露出区域(参照图3)。另外，钝化膜例如也可是SiO2或SiN等的无机绝缘膜。或者钝化膜16也可是聚酰亚胺树脂等的有机绝缘膜。
本实施方式相关的半导体装置，如图1所示，也可包括电极18。电极18也可沿边15的邻边19排列。电极18也可沿边19排列为一列。或者，电极18也可沿边19排列为多行多列。
如图1～图3所示，本实施方式相关的半导体装置包括形成在半导体芯片10上的树脂突起20。树脂突起20形成在半导体芯片10的形成电极14的面上。即树脂突起20也可形成在半导体芯片10的有源面上。树脂突起10也可形成在钝化膜16上。树脂突起20也可按照与集成电路12不重叠的方式形成。而且，树脂突起20也可避开电极14、18(使其露出那样)形成。另外，树脂突起20也可配置在电极14和边15之间。还有，树脂突起20也可配置在电极18和边19之间。即树脂突起20也可形成在半导体芯片10的有源面中、比电极14、18靠近外侧的区域。但是，本实施方式相关的半导体装置并不限于此。例如树脂突起20也可形成在比电极靠近内侧的区域。或者，树脂突起20也可配置为由多个电极14夹持。即也可在树脂突起20的两侧配置电极14。此时，如后文所述，布线32也可朝向树脂突起20的两侧而引出。换句话说，布线32也可从树脂突起20的两侧延伸。
树脂突起20的材料并不特别限定，也可适用已公知的任一种材料。例如树脂突起20也可由聚酰亚胺树脂、硅改性聚酰亚胺树脂、环氧树脂、硅改性环氧树脂、苯并环丁烯(BCB：benzocyclobutene)、聚苯并恶唑(PBO：polybenzoxazole)、酚醛树脂等的树脂形成。此外，树脂突起20的形状并不特别限定。例如树脂突起20也可形成为直线状(参照图1)。此时，树脂突起20也可按照沿半导体芯片10(半导体芯片10的有源面)的边延伸的方式形成。树脂突起20也可沿半导体芯片10的一条边一个一个地形成。或者，也可沿有源面的一条边形成多个树脂突起20(未图示)。还有，树脂突起20的表面也可形成曲面。此时，如图3所示，树脂突起20的剖面形状也可形成半圆状。但是，树脂突起20也可形成半球状(未图示)。
本实施方式相关的半导体装置包括多个电连接部30。电连接部30也可形成在树脂突起20上。电连接部30也可分别与电极14电连接。例如电连接部30也可指按照从电极14上引出到达树脂突起20的方式形成的布线32的一部分(与树脂突起20重叠的区域)。此时，所谓电连接部30也可指布线32中用于与外部电连接的部分。另外，如图1以及图2所示，也可在一个树脂突起20上形成多个电连接部30。此时，与电极14电连接的电连接部30也可形成在比电极14的排列的行数或列数小的数目的树脂突起20上。即如果将形成在一个树脂突起20上的电连接部30作为一个组，则与电极14电连接的电连接部30，也可按照能够划分为比电极14的排列的行数或列数小的组的方式形成。例如在树脂突起20形成与第一直线101平行延伸的形状时，树脂突起20也可形成为比第一直线101的数目少的数目。
布线32(电连接部30)的结构以及材料并没有特别限定。例如布线32也可形成为单层。或者，布线32也可形成多层。此时，布线32也可包括通过钛钨形成的第一层和由金形成的第二层(未图示)。
本实施方式相关的半导体装置1，也可具有以上的结构。而且，在图4中，半导体装置1表示安装在布线基板40上的样子。以下对此进行祥述。
首先，对布线基板40进行说明。布线基板40也可包括基底基板42和电连接部44。电连接部44也可指布线基板40的布线图案的一部分。即电连接部44也可指布线基板40的布线图案中、用于与外部电连接的部分。基底基板42的材料并不特别限定。也可利用由无机系材料形成的基板作为基底基板42。此时，基底基板42也可为陶瓷基板或玻璃基板。基底基板42为玻璃基板的情况下，布线基板40也可为电光学面板(液晶面板/电致发光面板等)的一部分。此时，电连接部44也可由ITO(Indium TinOxide)、Cr、Al等的金属膜、金属化合物膜、或者它们的复合膜形成。并且，电连接部44与驱动液晶的电极(扫描电极、信号电极、对置电极等)电连接。或者，基底基板42也可为由聚对苯二甲酸乙二醇酯(PET)构成的基板或薄膜。或者也可使用由聚酰亚胺树脂构成的柔性基板作为基底基板42。也可使用由FPC(Flexible Printed Circuit)或TAB(TapeAutomated Bonding)技术使用的带子作为柔性基板。此时，电连接部44也可层叠例如铜(Cu)、铬(Cr)、钛(Ti)、镍(Ni)、钛钨(Ti-W)中的任一个而形成。
并且，半导体装置1也可按照半导体芯片10的有源面与布线基板40对置的方式被搭载。此时，布线基板40的电连接部44与电连接部30也可进行接触而电连接。详细地来说，半导体装置1的电连接部30与布线基板40的电连接部44接触而电连接。由此，能够由树脂突起20的弹性力按压电连接部30和电连接部44。因此，能够提供电连接高可靠性的半导体装置。而且，半导体装置1也可通过粘接剂50与布线基板40粘接。半导体装置1也可通过粘接剂50固着在布线基板40上。也可通过粘接剂50保持半导体装置1和布线基板40之间的间隔，而维持树脂突起20弹性变形的状态。另外，半导体装置1也可直接安装在构成电子组件1000的玻璃基板上。此时半导体装置1也可以以称作COG(Chip On Glass)安装的方式对玻璃基板进行安装。
图5表示安装半导体装置1的电子组件1000。电子组件1000也可为显示设备。显示设备也可例如为液晶显示设备或EL(ElectricalLuminescence)显示设备。而且半导体装置1也可为控制显示设备的设备IC。
根据半导体装置1，可提供小型化且高可靠性的半导体装置。以下，对其进行详细说明。
以往，在安装半导体装置时，对电极施加力。并且，在按照电极与集成电路12的至少一部分重叠的方式配置的情况下，通过对电极施加力，会有集成电路12的特性变化的可能性。为了防止该现象，按照电极与集成电路不重叠的方式，将内部布线拉到半导体芯片的内侧。但是，随着半导体装置的微细化以及集成电路的高集成化，内部布线的拉回变难。而且，预想由于内部布线没有被拉回的原因，会对集成电路12的设计产生制约。
但是，如先前所说明那样，半导体装置1利用电连接部30作为外部端子。并且，电连接部30形成在树脂突起20上。因此，半导体装置1，能够不对电极14施加力而安装半导体装置。因此，根据本发明，即使在电极14形成在集成电路12上的情况下，在安装时也能提供集成电路12的特性没有变化的半导体装置。即根据本发明，即使在利用按照电极14与集成电路重叠的方式配置的半导体芯片的情况下，也能确保半导体装置的可靠性。
由此，根据本发明，能够提供可利用集成电路12的设计的制约小且集成电路12的设计自由度高的半导体芯片的半导体装置。而且，如果集成电路的设计自由度高，则可减小半导体芯片的外形。尤其如果能够将电极配置在集成电路之上，则能够使半导体芯片的外形进一步减小。因此，根据本发明，能够提供可利用外形小的半导体芯片的半导体装置。即根据本发明，能够提供外形小且高可靠性的半导体装置。此外，通过将电极14排列为多行多列，能够省空间地配置多个电极14。因此，还能提供外形小的半导体装置。
此外，通过将I/O单元排列为多行多列，能够使半导体芯片10进一步小型化。即通过将I/O单元排列为多行多列，能够减小I/O单元所占面积，同时可省空间地设计半导体芯片10的集成电路12。因此，可进一步使半导体芯片10小型化。此时，也可按照与I/O单元的至少一部分重叠的方式形成电极14。由此，不需要在I/O单元区域的外侧确保用于形成电极14的区域。此外，由此不需要连接I/O单元和电极14的布线区域。因此，可使半导体芯片10进一步小型化。另外，如先前所述，根据半导体装置1，能够对电极14不施加力地安装半导体装置。因此，即使在I/O单元上形成电极14的情况下，也可确保半导体装置的可靠性。
另外，根据半导体装置1，能够提供通用性高的半导体装置。详细地说，根据半导体装置1，即使电极14的排列(集成电路12的设计)不同的半导体芯片也可在相同位置形成电连接部30。因此，也可在一个布线基板上安装集成电路12的设计不同的半导体芯片。或者，即使具有相同设计的集成电路12的半导体芯片10也能改变电连接部30的排列。因此，可将形成相同集成电路的半导体芯片安装在不同设计的布线基板上。
图6为用于对适用本发明的实施方式的变形例相关的半导体装置进行说明的图。其中，图6为了简单，而省略了树脂突起20以及布线32(电连接部30)。本实施方式相关的半导体装置中，半导体基板10的电极60也可所有都配置在平行延伸的多条第一直线103和平行延伸的多条第二直线104之间的交点上。此时，如图6所示，第一以及第二直线103、104也可为正交的直线。此外，多条第一以及第二直线也可分别等间隔排列。详细地说，多条第一直线103也可等间隔排列。此外，多条第二直线104也可等间隔排列。此时，第一直线103与第二直线104也可以相同间隔排列。但是，第一以及第二直线也可为倾斜交叉的直线(未图示)。此时，未图示的树脂突起，也可配置在比电极60形成的区域更靠近外侧的区域内(仅)中。但是，也可在电极60形成的区域的内侧配置未图示的树脂突起。根据本实施方式，可提供高可靠性且小型化的半导体装置。
此外，适用本发明的实施方式的其他变形例，半导体装置也可形成具有晶圆状的半导体基板的结构(未图示)。此时，晶圆状的半导体基板包括形成多个半导体芯片10的区域。此外，晶圆状的半导体基板，在每个形成半导体芯片10的区域上形成制作上述的任一个构造的结构。由此，通过单个地切割晶圆状的半导体基板，能够提供具有半导体芯片10地上述任一个半导体装置。
另外，本发明并不限于上述的实施方式，有各种变形。例如，本发明包括与实施方式所说明的结构实质上相同的结构(例如功能、方法以及结果相同的结构或者目的以及效果相同的结构)。此外，本发明包括置换实施方式所说明的结构的非本质的部分的结构。此外，本发明包括能够实现与实施方式所说明的结构相同的作用效果或者达到相同目的的结构。此外，本发明包括在实施方式所说明的结构中添加公知技术的结构。

Claims (9)

1、一种半导体装置，其特征在于，包括：
形成有集成电路的半导体芯片；
形成在所述半导体芯片上且排列为多行多列的电极；
在所述半导体芯片的形成所述电极的面上形成的多个树脂突起；和
形成在所述树脂突起上且与所述多个电极电连接的多个电连接部。
2、根据权利要求1所述的半导体装置，其特征在于，
所述电极配置于平行延伸的多条第一直线和按照与所述第一直线正交的方式延伸的多条第二直线的各个交点。
3、根据权利要求2所述的半导体装置，其特征在于，
所述半导体芯片的外形为矩形，
所述第一及第二直线平行于所述半导体芯片的某个边而延伸。
4、根据权利要求1至3中任一项所述的半导体装置，其特征在于，
所述半导体芯片的外形为矩形，
所述树脂突起平行于所述半导体芯片的某个边而延伸。
5、根据权利要求4所述的半导体装置，其特征在于，
在所述半导体芯片的某个边的附近形成一个所述树脂突起。
6、根据权利要求4所述的半导体装置，其特征在于，
在所述半导体芯片的某个边的附近形成两个以上的所述树脂突起。
7、根据权利要求1至6中任一项所述的半导体装置，其特征在于，
在所述半导体芯片上形成有排列为多行多列的I/O单元，
各个所述电极与某个所述I/O单元电连接。
8、根据权利要求7所述的半导体装置，其特征在于，
各个所述电极按照与所对应的某个所述I/O单元的至少一部分重叠的方式形成。
9、根据权利要求1至8中任一项所述的半导体装置，其特征在于，
所述电极按照与所述集成电路的至少一部分重叠的方式形成。
CNB200610129069XA 2005-09-13 2006-09-08 半导体装置 Expired - Fee Related CN100524714C (zh)

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JP4572376B2 (ja) * 2007-07-30 2010-11-04 セイコーエプソン株式会社 半導体装置の製造方法および電子デバイスの製造方法
JP4352279B2 (ja) * 2007-08-21 2009-10-28 セイコーエプソン株式会社 半導体装置及びその製造方法
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JP6432737B2 (ja) 2015-03-04 2018-12-05 セイコーエプソン株式会社 Ｍｅｍｓデバイス、ヘッド及び液体噴射装置
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