TW200715530A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
TW200715530A
TW200715530A TW095132900A TW95132900A TW200715530A TW 200715530 A TW200715530 A TW 200715530A TW 095132900 A TW095132900 A TW 095132900A TW 95132900 A TW95132900 A TW 95132900A TW 200715530 A TW200715530 A TW 200715530A
Authority
TW
Taiwan
Prior art keywords
region
semiconductor chip
semiconductor device
electrodes
resin protrusions
Prior art date
Application number
TW095132900A
Other languages
English (en)
Inventor
Nobuaki Hashimoto
Original Assignee
Seiko Epson Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp filed Critical Seiko Epson Corp
Publication of TW200715530A publication Critical patent/TW200715530A/zh

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/525Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
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    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
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    • H01L24/02Bonding areas ; Manufacturing methods related thereto
    • H01L24/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
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    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
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    • H01L24/90Methods for connecting semiconductor or solid state bodies using means for bonding not being attached to, or not being formed on, the body surface to be connected, e.g. pressure contacts using springs or clips
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    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/563Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
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    • H01L2224/83192Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
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    • H01L2924/14Integrated circuits
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Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
TW095132900A 2005-09-13 2006-09-06 Semiconductor device TW200715530A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2005265484A JP4296434B2 (ja) 2005-09-13 2005-09-13 半導体装置

Publications (1)

Publication Number Publication Date
TW200715530A true TW200715530A (en) 2007-04-16

Family

ID=37549030

Family Applications (1)

Application Number Title Priority Date Filing Date
TW095132900A TW200715530A (en) 2005-09-13 2006-09-06 Semiconductor device

Country Status (5)

Country Link
US (1) US20070057370A1 (zh)
EP (1) EP1763076A3 (zh)
JP (1) JP4296434B2 (zh)
CN (1) CN100521174C (zh)
TW (1) TW200715530A (zh)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100816348B1 (ko) * 2005-09-13 2008-03-24 세이코 엡슨 가부시키가이샤 반도체 장치
JP4645635B2 (ja) 2007-11-02 2011-03-09 セイコーエプソン株式会社 電子部品
JP4888462B2 (ja) 2008-09-24 2012-02-29 セイコーエプソン株式会社 電子部品の実装構造
US11202370B2 (en) * 2017-10-23 2021-12-14 Boe Technology Group Co., Ltd. Integrated circuit chip, display apparatus, and method of fabricating integrated circuit chip

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2958136B2 (ja) * 1991-03-08 1999-10-06 株式会社日立製作所 半導体集積回路装置、その製造方法および実装構造
JPH05251455A (ja) * 1992-03-04 1993-09-28 Toshiba Corp 半導体装置
US5874782A (en) * 1995-08-24 1999-02-23 International Business Machines Corporation Wafer with elevated contact structures
TW324847B (en) * 1996-12-13 1998-01-11 Ind Tech Res Inst The structure of composite bump
TW478089B (en) * 1999-10-29 2002-03-01 Hitachi Ltd Semiconductor device and the manufacturing method thereof
DE10016132A1 (de) * 2000-03-31 2001-10-18 Infineon Technologies Ag Elektronisches Bauelement mit flexiblen Kontaktierungsstellen und Verfahren zu dessen Herstellung
JP3640876B2 (ja) * 2000-09-19 2005-04-20 株式会社ルネサステクノロジ 半導体装置及び半導体装置の実装構造体
JP3969295B2 (ja) * 2002-12-02 2007-09-05 セイコーエプソン株式会社 半導体装置及びその製造方法と回路基板及び電気光学装置、並びに電子機器

Also Published As

Publication number Publication date
JP4296434B2 (ja) 2009-07-15
EP1763076A2 (en) 2007-03-14
EP1763076A3 (en) 2009-09-16
US20070057370A1 (en) 2007-03-15
JP2007081042A (ja) 2007-03-29
CN100521174C (zh) 2009-07-29
CN1933137A (zh) 2007-03-21

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