CN1868058A - 用于减小或消除半导体器件引线偏移的系统和方法 - Google Patents
用于减小或消除半导体器件引线偏移的系统和方法 Download PDFInfo
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Abstract
提供一种封装半导体器件的方法。该方法包括:仅在多个导体中的至少两个导体的一部分上施加绝缘材料,所述多个导体在半导体器件中的元件之间提供互连。该方法还包括密封导体和元件,由此封装半导体器件。
Description
发明领域
本发明涉及封装半导体器件,尤其涉及设计减小和消除封装的半导体器件中的引线偏移(wire sweep)和倾斜(sway)的方法。
发明背景
在半导体器件的制造中,通常利用导体(例如,键合引线)来提供在半导体器件的元件之间的互连。例如,图1示出常规半导体器件100的一部分。半导体器件100包括引线框架102和引线框架触点102a。将半导体元件(例如,管芯)104安装在引线框架102上。键合引线106在半导体元件104与引线框架触点102a之间提供互连。在键合引线106、半导体元件104和引线框架触点102a上设置包覆模(overmold)108(即模塑化合物)。在图1所示的结构中,在半导体器件100中包含大量的键合引线106以在半导体元件104的各个连接点与相应的引线框架触点102a之间提供互连。
在半导体器件100的制造工艺期间,会在相邻的键合引线106之间发生短路或在与一条或多条键合引线106的连接中发生开路。例如,在制造期间,键合引线106的移动(例如,倾斜、偏移等)会导致相邻键合引线106之间的短路。
图2示出包含覆盖引线106的密封剂210的常规半导体器件200。密封剂210还覆盖键合引线106与半导体元件104和引线框架102a中的每一个之间的连接点。在其他方面,图2所示的元件与上述关于图1所示和所述的元件相似。
图3是与图1所示的器件相似的常规半导体器件100的透视图。示出半导体元件104安装在引线框架102上。多条键合引线106在半导体元件104与相应的引线框架触点102a之间提供互连。在半导体元件104和键合引线106上提供包覆模108(在图3中被部分切除)。
图4是常规半导体器件400的剖面侧视图。与在图1-3中一样,将半导体元件104安装在引线框架102上,并且键合引线106在半导体元件104与引线框架触点102a之间提供互连。在半导体元件104和键合引线106上提供密封剂410。在图4所示的半导体元件104的上面和下面提供包覆模108。
发现在图1-4所示的常规半导体器件结构中存在各种问题。如上面所提及的那样,在半导体器件的制造和移动期间,键合引线106在连接点之一(即在半导体元件104或引线框架触点102a)上可能变得松动(即开路)。此外,相邻的键合引线106可能朝向彼此移动(例如,倾斜),由此在半导体器件中造成短路。考虑到期望减小半导体器件的尺寸(并相应地期望增加半导体器件中的导体密度),这些情况就特别成问题。这些制造缺点会在批量半导体中产生有缺陷的器件,导致更高的制造成本和很差的可靠性。同样地,会期望提供一种改进的半导体器件的制造方法。
发明内容
为了克服现有技术的不足,在本发明的典型实施例中,提供一种封装半导体器件的方法。该方法包括仅在多个导体中的至少两个导体的一部分上施加绝缘材料,所述导体在半导体器件中的元件之间提供互连。该方法还包括密封导体和元件,由此封装半导体器件。
根据本发明的另一典型实施例,提供一种半导体器件。该半导体器件包括多个半导体元件、以及在多个半导体元件之间提供互连的多个导体。该半导体器件还包括仅在多个导体中的至少两个导体的一部分上所施加的绝缘材料。此外,该半导体器件包括密封导体和半导体元件的密封层,用于封装半导体器件。
附图简述
将参考附图来说明本发明的典型实施例,在附图中:
图1是现有技术的半导体器件中的半导体元件之间的互连的剖面侧视图;
图2是现有技术的半导体器件中的半导体元件之间的密封互连的剖面侧视图;
图3是现有技术的半导体器件中的半导体元件之间的多个互连的透视图;
图4是现有技术的半导体器件中的半导体元件之间的密封互连的剖面侧视图;
图5是根据本发明的典型实施例的半导体器件中的半导体元件之间的互连的剖面侧视图;
图6是根据本发明的另一典型实施例的半导体器件中的半导体元件之间的互连的剖面侧视图;
图7是根据本发明的典型实施例的半导体器件中的半导体元件之间的互连的透视图;
图8是根据本发明的另一典型实施例的半导体器件中的半导体元件之间的互连的透视图;
图9是由根据本发明的典型实施例的绝缘材料分开的导体的剖面侧视图;
图10是示出根据本发明的典型实施例的绝缘材料中的硅石颗粒尺寸分布的图表;
图11是示出根据本发明的另一典型实施例的绝缘材料中的硅石颗粒尺寸分布的图表;以及
图12是示出封装根据本发明的典型实施例的半导体器件的方法的流程图。
发明的详细说明
现在将参考附图说明本发明的所选实施例的优选特征。应该理解的是本发明的精神和范围不限于为说明而选择的实施例。同样,应该注意的是没有按照特定的刻度或比例来绘制附图。应该想到可以在本发明的范围内修改下文中所述的任何结构和材料。
如在本文中所使用的那样,术语半导体器件涉及范畴很广的器件,其包括封装的半导体器件,例如集成电路、存储器件、DSP(即数字信号处理器)、QFP(即四平封装)、PBGA(即塑料球栅阵列)、BOC(板级芯片(board on chip))、COB(即板上芯片)、CABGA(芯片阵列球栅阵列);以及分立器件(即未封装的器件,在一个电路板上可以有不止一个器件)。此外,术语半导体元件指的是半导体器件的任何部分,包括衬底、管芯、芯片、引线框架、引线框架触点等。
一般来讲,本发明涉及在键合导体(即键合引线)上设置绝缘材料(例如,采用聚合物珠、条或预先形成的形状的形式),所述键合导体在半导体器件中的各个半导体元件之间提供互连。
绝缘材料(例如,聚合物桥)产生将为导体提供额外的稳定性从而在进一步的处理过程中(例如在转移模塑过程中)使导体分开(即没有短路)的晶格(晶格桥)或结构。此外,如果将绝缘材料以至少部分为流体的状态进行施加,则在半导体器件的模塑过程中,其可以通过流体力而分布在整个互连导体网中。这种分开和力转移减小了引线偏移和倾斜,并且减小或消除由包覆模工艺所引起的短路。
在施加绝缘材料(例如,诸如环氧树脂的聚合物材料)之后,利用热能或紫外线能中的至少一种来固化树脂。然后可以施加包覆模以提供封装的半导体器件,而使引线不会朝向彼此移动或“偏移”。
根据本发明的特定实施例,本文中公开的方法和器件特别适合于按照合同并由集成器件制造商(by contract and integrated devicemanufacturer)制造的键合引线半导体器件的组装。对于具有长导体/键合引线或具有复杂的键合引线几何形状(例如,QFP、层叠的管芯器件和BGA)的半导体器件,本发明的特定实施例是特别有用。
与现有技术的制造方法相反,本发明的各个实施例在包含在半导体器件中的半导体元件周围或附近以环形、矩形和/或任何适当的结构来利用非常少量的绝缘材料(例如聚合物材料)。
如本文所述,与现有制造技术相比本发明的特定实施例具有额外的优点,包括:制造工艺中的额外灵活性、用于稳定导体的昂贵聚合物的最小化、以及通用半导体器件的应用。本发明的典型实施例减小了复杂半导体器件类型(例如,层叠的管芯器件)上的偏移,并且允许例如在QFP和BGA中延长导体长度。
图5示出根据本发明的典型实施例的半导体器件500的剖面侧视图。半导体器件500包括安装在引线框架502上的半导体元件504(例如,管芯)。例如,可以利用粘合剂将半导体元件504安装到引线框架502上。键合引线506在半导体元件504与引线框架触点502a之间提供互连。在将包覆模508施加到器件之前,将绝缘材料512施加到键合引线506的一部分上。例如,可以在半导体元件504的周围或附近以矩形、环形和/或任何适当的形状来施加绝缘材料512。此外,可以将绝缘材料512设置成更接近于半导体元件504(与引线框架触点502a相对),因为键合引线506在半导体元件504处比在引线框架触点502a处具有更近的引线间距(即,更接近于相邻引线506)。或者,可以将绝缘材料512设置在半导体元件504和引线框架触点502a的中间。此外,可以将绝缘材料512设置在半导体元件504和引线框架触点502a之间的大量位置中的任意处,如在特定器件中所期望的那样。
通过在键合引线506上提供绝缘材料512,来稳定键合引线506中的每一条相对于彼此的位置。通过利用绝缘材料512来使键合引线506相对于彼此保持稳定,则即使没有消除也会大大减小在施加包覆模508过程中使相邻键合引线506短路的风险。另外,通过稳定键合引线506的位置,还可以大大减小在制造期间键合引线506的开路。
例如,绝缘材料512可以是诸如环氧树脂的聚合物材料。另外,绝缘材料512可以包括在将绝缘材料512施加到键合引线506期间分布在键合引线506之间的绝缘颗粒或小珠。这种绝缘小珠也使键合引线506相对于彼此稳定。根据本发明的典型实施例,分布在绝缘材料中的绝缘小珠具有近似为4.1μm的平均粒径、4.5μm的中值粒径、和20μm的最大粒径。例如,这些绝缘小珠可以是球形的硅石颗粒。
图6是半导体器件600的剖面侧视图,其中半导体器件600与图5所示的半导体器件500相似。如与图5所示的本发明的典型实施例一样,图6示出设置在键合引线506的一部分上的绝缘材料512。然而,除绝缘材料512之外,图6还示出设置在键合引线506的另一部分上的绝缘材料514。可以以与绝缘材料512相似的结构(例如,在半导体元件504的周围或附近以矩形、环形和/或任何适当的形状)来设置绝缘材料514。另外,绝缘材料514可以是诸如环氧树脂的聚合物材料,并且可以包括如参考图5所述的绝缘小珠。
图7示出包含安装在引线框架702上的半导体元件704的半导体器件700。键合引线706在半导体元件704与引线框架触点702a之间提供互连。将绝缘材料712设置在键合引线706的一部分上以使键合引线706相对于彼此稳定。在图7所示的典型实施例中,在半导体元件704周围或附近以基本上为环形的形状(和/或任何适当的形状)来设置键合引线706。通过将绝缘材料712设置在键合引线706的一部分上,在施加包覆模708之前和期间,可以大大减小键合引线706的开路或短路。
图8是与图7所示的器件相似的半导体器件800的透视图。除图7中所提供的环状绝缘材料712之外,图8示出设置在键合引线706的一部分上的绝缘材料814。通过提供除绝缘材料712之外的绝缘材料814,使键合引线706进一步相对于彼此稳定。
虽然图7示出包含单个绝缘材料环712的半导体器件700,并且图8示出包含绝缘材料环712和绝缘材料环814的半导体器件800,但是可以提供额外的绝缘材料环(或其他形状部分)。同样,可以将一个、两个、三个或任意数量的绝缘材料环/小珠施加到特定的半导体器件上,如所期望的那样。
图9是键合引线906a、906b和906c的剖面侧视图。例如,键合引线906a、906b和906c在半导体器件中的半导体元件(在图9中未示出)和引线框架触点(在图9中未示出)之间提供互连。将绝缘材料912设置在键合引线906a、906b和906c的一部分上。在图9所示的本发明的典型实施例中,绝缘材料912包括绝缘小珠。绝缘小珠可以具有各种不同的尺寸,并且因为绝缘小珠小于相邻键合引线之间(例如,键合引线906a与906b之间)的距离,所以绝缘小珠分散到相邻键合引线之间的位置中,由此在相邻的键合引线之间提供增强的稳定性和绝缘性。
图9示出表示键合引线906a与906b之间的中心至中心的距离(即,引线间距)的距离“d1”。此外,图9示出表示键合引线906a与906b之间的间隔的距离“d2”。根据本发明的典型实施例,可以将绝缘材料施加到引线间距非常细微的键合引线的半导体器件。例如,这种器件中的距离d1大约为35μm或以下,而这种器件中的距离d2可以大约为15μm或以下。通过将绝缘材料(例如,具有分散在其中的绝缘小珠)设置在键合引线的一部分上,可以将本发明的改进的键合引线稳定性应用于距离d1和d2的值很小的引线间距非常细微的键合引线的半导体器件。
通过根据本文中所述的方法制造半导体器件,可以增加半导体器件内的导体密度,令人满意地使半导体器件的尺寸减小。
根据本发明制造半导体器件的另一优点是:由于包括键合引线的一部分上的绝缘材料,所以用于密封器件的包覆模/密封材料可以由不太昂贵的材料和工艺(例如与“小滴封顶(glob-topping)”相对的模塑型密封)来构造,因为不必由密封剂来稳定键合引线。
包含在根据本发明的各典型实施例所采用的绝缘材料中的小珠可以是各种绝缘小珠类型中的任何一种。例如,小珠可以由硅石填充剂来构成。此外,绝缘小珠可以是具有变化的尺寸和形状的各种类型。
本发明的绝缘材料可以包括高粘性、可紫外线固化的硅石。例如,可以以50-85%之间的重量百分比来利用硅石填充绝缘材料。
图10是示出在根据本发明的典型实施例的绝缘材料中使用的两种截然不同的硅石填充剂(例如,SiO2)的典型颗粒大小(即,颗粒直径)分布的柱形统计图表。在图10所示的典型分布中,硅石2的小珠的颗粒大小的范围从大约0.05微米到大约0.5微米。此外,硅石1的小珠的颗粒大小的分布范围从大约0.5微米到大约20微米。图10的柱形统计图表的y-轴示出硅石1颗粒和硅石2颗粒中的每一种的各个尺寸的百分比。
已经证明图10中示出的硅石填充剂当被分散在根据本发明的特定典型实施例的绝缘材料(例如,环氧树脂)中时特别有利。对于指定为硅石1的球形硅石类型,单独的硅石直径大小的分布为:0%大于24微米;1.1%小于24微米而大于16微米;4.0%小于16微米而大于12微米;11.5%小于12微米而大于8微米;12.8%小于8微米而大于6微米;35.8%小于6微米而大于3微米;13.3%小于3微米而大于2微米;12.5%小于2微米而大于1微米;7.0%小于1微米而大于0.5微米,以及2.0%小于0.5微米而大于0微米。对于指定为硅石2的球形硅石类型,单独的硅石直径大小的分布为:0%大于0.6微米;0.5%小于0.6微米而大于0.5微米;7.03%小于0.5微米而大于0.45微米;9.13%小于0.45微米而大于0.4微米;12.83%小于0.4微米而大于0.35微米;13.43%小于0.35微米而大于0.3微米;13.33%小于0.35微米而大于0.3微米;9.33%小于0.3微米而大于0.25微米;5.83%小于0.25微米而大于0.2微米,4.33%小于0.2微米而大于0.15微米;5.83%小于0.15微米而大于0.1微米,5.93%小于0.1微米而大于0.09微米;5.53%小于0.09微米而大于0.08微米,4.93%小于0.08微米而大于0.07微米;1.73%小于0.07微米而大于0.06微米,以及0.31%小于0.06微米。
如上所提及的那样,可以将不同类型和尺寸的绝缘小珠(例如,硅石颗粒)混合在根据本发明的特定典型实施例的绝缘材料中。例如,以硅石1分布的颗粒可以与以硅石2分布的颗粒混合。在一个实施例中,将10份的以硅石1分布的颗粒与3份的以硅石2分布的颗粒混合。在图11中提供示出这种混合物的SiO2颗粒大小分布的柱形统计图表。
对于图11所示的球形硅石的混合物,硅石直径大小的单独分布为:0%大于24微米;0.85%小于24微米而大于16微米;3.08%小于16微米而大于12微米;8.85%小于12微米而大于8微米;9.85%小于8微米而大于6微米;27.54%小于6微米而大于3微米;10.23%小于3微米而大于2微米;9.62%小于2微米而大于1微米;5.5%小于1微米而大于0.6微米;3.16%小于0.6微米而大于0.5微米;2.11%小于0.5微米而大于0.45微米;2.96%小于0.45微米而大于0.4微米;3.1%小于0.4微米而大于0.35微米;3.08%小于0.35微米而大于0.3微米;2.15%小于0.3微米而大于0.25微米;1.35%小于0.25微米而大于0.2微米;1.0%小于0.2微米而大于0.15微米;1.35%小于0.15微米而大于0.1微米;1.37%小于0.1微米而大于0.09微米;1.28%小于0.09微米而大于0.08微米;1.14%小于0.08微米而大于0.07微米;0.4%小于0.07微米而大于0.06微米;0.07%小于0.06微米而大于0.05微米;以及0%小于0.05微米。
图12是示出封装半导体器件的方法的流程图。在步骤1202,仅在多个导体中的至少两个导体的一部分上施加绝缘材料,所述多个导体在半导体器件中的元件之间提供互连。在步骤1204,密封导体和半导体元件,由此封装半导体器件。在可选步骤1206,在施加步骤之后将绝缘材料固化。
虽然已经主要针对在包含在半导体器件中的半导体元件周围或者附近的环形或矩形绝缘材料,对本发明进行了说明,但本发明不限于此。可以以各种结构(例如,绝缘材料的线性桥)来提供绝缘材料,只要稳定导体以减小引线偏移就行。
此外,可以在半导体器件的内部元件周围以基本上呈环绕的形状来施加绝缘化合物。基本上呈环绕的形状可以是大量几何形状中的任何一种,例如环形、圆形、椭圆形、正方形或长方形。此外,由于几何形状基本上呈环绕状,因此不必完全包围半导体器件的内部元件。
虽然已经主要针对绝缘材料是诸如环氧树脂的聚合物材料的情况,对本发明进行了说明,但本发明不限于此。可以利用各种可选的绝缘材料,只要该材料为在半导体器件的元件之间提供互连的导体提供稳定性就行。例如,可以将具有粘合性衬背(adhesive backing)的固态或基本为固态的绝缘体设置到键合引线的一部分上,由此稳定键合引线并且大大减小了在相邻的键合引线当中产生短路的可能性。或者,可以将绝缘胶带施加到键合引线的一部分上,同样可以稳定键合引线并且大大减小了在相邻的键合引线当中产生短路的可能性。
在绝缘材料中包含绝缘颗粒的本发明的实施例中,已经主要针对硅石颗粒,对所述颗粒进行了说明;然而,所述颗粒并不限于此。在绝缘材料中可以利用各种可选的颗粒或小珠,只要颗粒可以分散在相邻的导体之间就行,其中所述导体在半导体器件的元件之间提供互连。
应该理解的是,在不脱离本发明范围的情况下可以对所示的实施例进行其他修改,本发明的范围被单独地限定在附属的权利要求中。
Claims (23)
1、一种封装半导体器件的方法,该方法包括以下步骤:
仅在多个导体中的至少两个导体的一部分上施加绝缘材料,所述多个导体在所述半导体器件中的元件之间提供互连;以及
密封所述导体和所述元件,由此封装所述半导体器件。
2、根据权利要求1所述的方法,还包括以下步骤:
在所述施加步骤之后固化所述绝缘材料。
3、根据权利要求2所述的方法,其中所述固化步骤包括加热所述绝缘材料和将所述绝缘材料暴露给UV辐射中的至少一种。
4、根据权利要求1所述的方法,其中所述施加步骤包括将包含球形硅石颗粒的绝缘化合物施加到多个导体的所述部分上。
5、根据权利要求4所述的方法,其中在所述半导体器件的内部元件附近,以大体环绕的方式施加所述绝缘化合物。
6、根据权利要求4所述的方法,其中以至少两种几何形状结构来施加所述绝缘化合物,所述几何形状结构中的每一种以环绕的方式基本包围所述半导体器件的内部元件。
7、根据权利要求1所述的方法,其中所述施加步骤包括将具有粘合性衬背的固态绝缘体施加到多个导体的所述部分上,从而所述粘合性衬背与多个导体的所述部分接触。
8、根据权利要求1所述的方法,其中所述施加步骤包括将绝缘胶带施加到多个导体的所述部分上。
9、根据权利要求1所述的方法,其中所述施加步骤包括仅在多个导体中的至少两个导体的一部分上施加所述绝缘材料的连续小珠,所述多个导体在所述半导体器件中的元件之间提供互连。
10、根据权利要求1所述的方法,其中所述施加步骤包括在所述半导体器件的内部元件的外围部分周围施加所述绝缘材料。
11、根据权利要求1所述的方法,其中所述施加步骤包括在所述半导体器件的内部元件的外围部分周围以至少两种截然不同的结构来施加所述绝缘材料,所述两种结构彼此不接触。
12、一种半导体器件,包括:
多个半导体元件;
多个导体,在所述多个半导体元件之间提供互连;以及
仅在所述多个导体中的至少两个导体的一部分上施加的绝缘材料。
13、根据权利要求12所述的半导体器件,还包括密封所述导体和元件的密封层,用于封装所述半导体器件。
14、根据权利要求12所述的半导体器件,其中所述多个半导体元件包括:至少一个具有多个第一触点的半导体管芯;以及具有多个第二触点的引线框架,所述多个导体在所述多个第一触点与所述多个第二触点之间提供互连。
15、根据权利要求14所述的半导体器件,其中在所述多个导体中的所述至少两个导体的与所述半导体管芯相邻的所述部分上设置所述绝缘材料。
16、根据权利要求14所述的半导体器件,其中在所述多个导体中的所述至少两个导体的大约处在所述半导体管芯与所述引线框架之间的中间位置处的所述部分上设置所述绝缘材料。
17、根据权利要求12所述的半导体器件,其中所述绝缘材料是可固化的绝缘材料。
18、根据权利要求12所述的半导体器件,其中所述绝缘材料是热感应可固化绝缘材料和UV辐射可固化绝缘材料中的至少一种。
19、根据权利要求12所述的半导体器件,其中所述绝缘材料由多个球形硅石颗粒组成。
20、根据权利要求12所述的半导体器件,其中在所述半导体器件的内部元件的外围部分周围施加所述绝缘材料。
21、根据权利要求12所述的半导体器件,其中在所述半导体器件的内部元件的外围部分周围以至少两种截然不同的结构来施加所述绝缘材料,所述两种结构彼此不接触。
22、根据权利要求12所述的半导体器件,其中所述绝缘材料包括具有粘合性部件的基本上为固态的绝缘体,从而所述粘合性部件与所述多个导体中的所述至少两个导体的所述部分接触。
23、根据权利要求12所述的半导体器件,其中所述绝缘材料为绝缘胶带。
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Application Number | Priority Date | Filing Date | Title |
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US10/686,974 | 2003-10-16 | ||
US10/686,974 US6955949B2 (en) | 2003-10-16 | 2003-10-16 | System and method for reducing or eliminating semiconductor device wire sweep |
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CN1868058A true CN1868058A (zh) | 2006-11-22 |
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CNA2004800302203A Pending CN1868058A (zh) | 2003-10-16 | 2004-06-07 | 用于减小或消除半导体器件引线偏移的系统和方法 |
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US (2) | US6955949B2 (zh) |
JP (1) | JP2007509491A (zh) |
KR (1) | KR20060098382A (zh) |
CN (1) | CN1868058A (zh) |
TW (1) | TW200515517A (zh) |
WO (1) | WO2005041298A1 (zh) |
Families Citing this family (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20060043612A1 (en) * | 2004-09-02 | 2006-03-02 | Stats Chippac Ltd. | Wire sweep resistant semiconductor package and manufacturing method thereof |
TWI247367B (en) * | 2004-12-02 | 2006-01-11 | Siliconware Precision Industries Co Ltd | Semiconductor package free of carrier and fabrication method thereof |
US8035205B2 (en) * | 2007-01-05 | 2011-10-11 | Stats Chippac, Inc. | Molding compound flow controller |
US7612444B2 (en) * | 2007-01-05 | 2009-11-03 | Stats Chippac, Inc. | Semiconductor package with flow controller |
US8536717B2 (en) * | 2012-01-10 | 2013-09-17 | Xilinx, Inc. | Integrated circuit package and method of assembling an integrated circuit package |
US8912667B2 (en) * | 2012-01-31 | 2014-12-16 | Freescale Semiconductor, Inc. | Packaged integrated circuit using wire bonds |
US8680660B1 (en) * | 2013-03-12 | 2014-03-25 | Freescale Semiconductor, Inc. | Brace for bond wire |
US9613877B2 (en) | 2013-10-10 | 2017-04-04 | UTAC Headquarters Pte. Ltd. | Semiconductor packages and methods for forming semiconductor package |
CN105206596B (zh) | 2014-06-06 | 2018-12-07 | 恩智浦美国有限公司 | 具有弯折引线的封装集成电路器件 |
US11056457B2 (en) | 2018-09-28 | 2021-07-06 | Nxp Usa, Inc. | Semiconductor device with bond wire reinforcement structure |
Family Cites Families (25)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5623759A (en) | 1979-08-01 | 1981-03-06 | Hitachi Ltd | Resin-sealed semiconductor device and manufacture thereof |
JPS6331149A (ja) | 1986-07-25 | 1988-02-09 | Fujitsu Ltd | 半導体装置 |
US4974057A (en) | 1986-10-31 | 1990-11-27 | Texas Instruments Incorporated | Semiconductor device package with circuit board and resin |
JP2712618B2 (ja) | 1989-09-08 | 1998-02-16 | 三菱電機株式会社 | 樹脂封止型半導体装置 |
JPH03229433A (ja) | 1990-02-02 | 1991-10-11 | Matsushita Electric Ind Co Ltd | 半導体素子 |
US5206794A (en) | 1991-12-20 | 1993-04-27 | Vlsi Technology, Inc. | Integrated circuit package with device and wire coat assembly |
US5331205A (en) | 1992-02-21 | 1994-07-19 | Motorola, Inc. | Molded plastic package with wire protection |
US5310702A (en) | 1992-03-20 | 1994-05-10 | Kulicke And Soffa Industries, Inc. | Method of preventing short-circuiting of bonding wires |
US5656830A (en) | 1992-12-10 | 1997-08-12 | International Business Machines Corp. | Integrated circuit chip composite having a parylene coating |
JP3400548B2 (ja) | 1993-06-29 | 2003-04-28 | 三菱レイヨン株式会社 | 高純度球状シリカの製造方法 |
US5434105A (en) | 1994-03-04 | 1995-07-18 | National Semiconductor Corporation | Process for attaching a lead frame to a heat sink using a glob-top encapsulation |
JPH0837252A (ja) | 1994-07-22 | 1996-02-06 | Nec Corp | 半導体装置 |
US5736792A (en) * | 1995-08-30 | 1998-04-07 | Texas Instruments Incorporated | Method of protecting bond wires during molding and handling |
JPH1187424A (ja) | 1997-09-10 | 1999-03-30 | Hitachi Ltd | 半導体装置およびその製造方法 |
US6297078B1 (en) | 1997-12-31 | 2001-10-02 | Intel Corporation | Integrated circuit package with bond wires at the corners of an integrated circuit |
JP2000063630A (ja) | 1998-08-21 | 2000-02-29 | Nippon Chem Ind Co Ltd | 微細球状シリカ及び液状封止樹脂組成物 |
US6177726B1 (en) | 1999-02-11 | 2001-01-23 | Philips Electronics North America Corporation | SiO2 wire bond insulation in semiconductor assemblies |
JP2000332165A (ja) | 1999-05-17 | 2000-11-30 | Toray Ind Inc | 半導体封止用樹脂組成物およびそれを用いた半導体装置 |
JP2001068802A (ja) | 1999-08-31 | 2001-03-16 | Kyocera Corp | 配線基板用絶縁シートおよびそれを用いた配線基板の製造方法 |
JP3765952B2 (ja) | 1999-10-19 | 2006-04-12 | 富士通株式会社 | 半導体装置 |
US6368899B1 (en) | 2000-03-08 | 2002-04-09 | Maxwell Electronic Components Group, Inc. | Electronic device packaging |
US6344401B1 (en) | 2000-03-09 | 2002-02-05 | Atmel Corporation | Method of forming a stacked-die integrated circuit chip package on a water level |
US6340846B1 (en) | 2000-12-06 | 2002-01-22 | Amkor Technology, Inc. | Making semiconductor packages with stacked dies and reinforced wire bonds |
JP2002368029A (ja) | 2001-06-06 | 2002-12-20 | Hitachi Ltd | 半導体装置の製造方法 |
US6608390B2 (en) | 2001-11-13 | 2003-08-19 | Kulicke & Soffa Investments, Inc. | Wirebonded semiconductor package structure and method of manufacture |
-
2003
- 2003-10-16 US US10/686,974 patent/US6955949B2/en not_active Expired - Fee Related
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2004
- 2004-05-26 TW TW093114871A patent/TW200515517A/zh unknown
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- 2004-06-07 WO PCT/US2004/017981 patent/WO2005041298A1/en active Application Filing
- 2004-06-07 JP JP2006535324A patent/JP2007509491A/ja not_active Withdrawn
- 2004-06-07 KR KR1020067009411A patent/KR20060098382A/ko not_active Application Discontinuation
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2005
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US20050085019A1 (en) | 2005-04-21 |
JP2007509491A (ja) | 2007-04-12 |
TW200515517A (en) | 2005-05-01 |
KR20060098382A (ko) | 2006-09-18 |
US20050224930A1 (en) | 2005-10-13 |
US6955949B2 (en) | 2005-10-18 |
US7109586B2 (en) | 2006-09-19 |
WO2005041298A1 (en) | 2005-05-06 |
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