JPH03229433A - 半導体素子 - Google Patents

半導体素子

Info

Publication number
JPH03229433A
JPH03229433A JP2024931A JP2493190A JPH03229433A JP H03229433 A JPH03229433 A JP H03229433A JP 2024931 A JP2024931 A JP 2024931A JP 2493190 A JP2493190 A JP 2493190A JP H03229433 A JPH03229433 A JP H03229433A
Authority
JP
Japan
Prior art keywords
conductive wire
resin
bonding
semiconductor device
bonded
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2024931A
Other languages
English (en)
Inventor
Akiyoshi Kawazu
河津　明美
Hikari Fujita
光 藤田
Yoshiro Maki
牧　芳郎
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP2024931A priority Critical patent/JPH03229433A/ja
Publication of JPH03229433A publication Critical patent/JPH03229433A/ja
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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    • H01L2224/4805—Shape
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    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
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    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
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    • H01L2224/49175—Parallel arrangements
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    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【発明の詳細な説明】 産業上の利用分野 この発明は半導体素子に係り、特に電極とインナーリー
ドを接続する、改良された導電性ワイヤーを有する半導
体素子に係わる。
従来の技術 半導体装置の組立には、半導体素子の電極とイ〉ナーリ
ードとを導電性ワイヤーで接続するボンディング工程が
ある。
第３図に示すように半導体素子１を銀（Ａ　ｇ　）ペー
スト６等のマウント剤によりリードフレーム２に固着し
た後、この半導体素子１の電極（図示せず）と導電性ワ
イヤー４の一端とをボンディング接続し　しかる後この
導電性ワイヤー４の他端とリードフレーム２のインナー
リード部３とをボンディング接続する。ここで半導体素
子１はシリコン（Ｓｉ）、半導体素子１の電極部は一般
にアルミニューム（Ａｘ）、インナーリード３は鉄（Ｆ
ｅ）系または１（Ｃｕ）系の材料で構成され　ボンディ
ング部には通常金（Ａ　ｕ　）めっきが施されている。
また導電性ワイヤー４として１よ　金（Ａ　ｕ　）やア
ルミニューム（Ａｘ）または銅（Ｃｕ）の細線が用いら
れている。な抵　ボンディング方法として（よ熱圧着法
又は超音波法が一般に用いられている。
このように導電性ワイヤーでボンディング接続されたの
板　破線で示すモールド樹脂５により樹脂モールド又は
気密封止することにより半導体装置の組立か行なわれる
。
発明か解決しようとする課題 前記半導体素子は一枚のウェハーから多数）素子をダイ
シング等の手段により割断されている。
素子表面は酸化膜または窒化膜等の絶縁膜か形成されて
いる力（割断された面及びそのエツジはサブストレート
のシリコンが露出している。上記ボンディング工程後の
導電性ワイヤーは金属であるため第２図（ａ）の円８内
に示すように前記素子１のエツジと導電性ワイヤー４の
接触による短絡不良がしばしば発生する。また近年の高
密度化に伴いリード間距離も極めて短くなり、第２図（
ｂ）に示すように導電性ワイヤー４のたる収　傾き等の
原因による導電性ワイヤー４間の短絡不良も発生してい
る。
特にワイヤーボンディング後の工程において、例えばリ
ードフレームを移動させる際に衝撃　振動か生じること
により、導電性ワイヤー４のたるへ　傾き等の変形が発
生し　導電性ワイヤー４間の知育、＆　　エツジタッチ
等の不良を引き起こす原因ともなる。この様に導電性ワ
イヤー４を露出した状態は短絡　断線等の不良原因とな
り、後工程において設備や部品の管理が困難となり、更
に部品の信頼性低下の原因ともなる。
課題を解決するための手段 本発明は　ボンディング接続する導電性ワイヤーに紫外
線硬化性樹脂を塗布しボンディング後に紫外線を照射し
　樹脂を硬化することにより導電性ワイヤーのみに均一
に絶縁性樹脂のコーティングを行なう。
作用 本発明によれＩＬ　　樹脂でコーティングされた導電性
ワイヤーか補強され衝撃　振動にたいしても変形しない
良好な強度が保たれる。また仮にサブストレートのエツ
ジまたは他の導電性ワイヤーと接触しても樹脂コーティ
ングにより絶縁されているた取　短絡不良は発生しなｌ
、％ 実施例 以下本発明の実施例を図面に基づいて説明する。
第１図は本発明の実施例におけるボンディング工程の終
了した半導体装置の断面図であり、　リードフレーム２
には銀ペースト６により半導体素子１か固着されている
。半導体素子ｌの電極には例えば金線の導電性ワイヤー
４の一端かボンディング接続され　この導電性ワイヤー
４の他端はインナーリード３の表面にボンディング接続
されている。
この導電性ワイヤー４の表面には絶縁性樹脂７が均一に
コーティングされている。この絶縁性樹脂７としては紫
外線硬化型の例えばアクリル系接着樹脂を用いている。
導電性ワイヤー４としては柔軟性が必要である為前記接
着樹脂は液状態で導電性ワイヤーのボンディング中に導
電性ワイヤー表面に均一に塗布しボンディング終了後に
紫外線を照射し接着樹脂を硬化すム　硬化した樹脂は機
械的強度及び電気的絶縁性を保有する。従って、その後
の工程において振軌　衝撃か生じても導電性ワイヤー４
が変形もしくは断線することなく、又仮に半導体素子１
のサブストレートのエツジもしくは他の導電性ワイヤー
と接触して秋　絶縁性樹脂７により絶縁されているため
短絡不良は発生しない。
発明の効果 以上のように本発明によれｔ′Ｌ　半導体素子とインキ
−リードとの接続において短絡不良または断線不良のな
し＼　信頼性の優れた半導体素子が得られると言う効果
がある。
【図面の簡単な説明】
第１図は本発明の実施例に係る半導体素子のボンディン
グ工程終了後の要部断面図　第２＠　第３図は従来の半
導体素子の要部断面図である。 １・・・半導体素子、　２・・・リードフレーム３・・
・インナーリード、　４・・・導電性ワイヤ５・・・モ
ールド樹脂　６・・・銀ペースト、７・・・絶縁性樹ｆ
ｌ’Ｂ。

Claims (1)

    【特許請求の範囲】
  1. 半導体素子の電極とインナーリードが導電性ワイヤーで
    接続された半導体素子において、前記導電性ワイヤーの
    みを紫外線硬化樹脂によりコーティングしたことを特徴
    とする半導体素子。
JP2024931A 1990-02-02 1990-02-02 半導体素子 Pending JPH03229433A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2024931A JPH03229433A (ja) 1990-02-02 1990-02-02 半導体素子

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2024931A JPH03229433A (ja) 1990-02-02 1990-02-02 半導体素子

Publications (1)

Publication Number Publication Date
JPH03229433A true JPH03229433A (ja) 1991-10-11

Family

ID=12151837

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2024931A Pending JPH03229433A (ja) 1990-02-02 1990-02-02 半導体素子

Country Status (1)

Country Link
JP (1) JPH03229433A (ja)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2005041298A1 (en) * 2003-10-16 2005-05-06 Kulicke & Soffa Investments, Inc. System and method for reducing or eliminating semiconductor device wire sweep
US7179688B2 (en) 2003-10-16 2007-02-20 Kulicke And Soffa Industries, Inc. Method for reducing or eliminating semiconductor device wire sweep in a multi-tier bonding device and a device produced by the method

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2005041298A1 (en) * 2003-10-16 2005-05-06 Kulicke & Soffa Investments, Inc. System and method for reducing or eliminating semiconductor device wire sweep
US6955949B2 (en) 2003-10-16 2005-10-18 Kulicke & Soffa Investments, Inc. System and method for reducing or eliminating semiconductor device wire sweep
US7109586B2 (en) 2003-10-16 2006-09-19 Kulicke And Soffa Industries, Inc. System for reducing or eliminating semiconductor device wire sweep
US7179688B2 (en) 2003-10-16 2007-02-20 Kulicke And Soffa Industries, Inc. Method for reducing or eliminating semiconductor device wire sweep in a multi-tier bonding device and a device produced by the method

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