CN1085409C - 底部引线的半导体封装件 - Google Patents

底部引线的半导体封装件 Download PDF

Info

Publication number
CN1085409C
CN1085409C CN97109573A CN97109573A CN1085409C CN 1085409 C CN1085409 C CN 1085409C CN 97109573 A CN97109573 A CN 97109573A CN 97109573 A CN97109573 A CN 97109573A CN 1085409 C CN1085409 C CN 1085409C
Authority
CN
China
Prior art keywords
lead
semiconductor package
package part
pad
bottom lead
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
CN97109573A
Other languages
English (en)
Other versions
CN1164764A (zh
Inventor
朴桂灿
卢吉燮
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
SK Hynix Inc
Original Assignee
Hyundai Electronics Industries Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hyundai Electronics Industries Co Ltd filed Critical Hyundai Electronics Industries Co Ltd
Publication of CN1164764A publication Critical patent/CN1164764A/zh
Application granted granted Critical
Publication of CN1085409C publication Critical patent/CN1085409C/zh
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49866—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers characterised by the materials
    • H01L23/49883—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers characterised by the materials the conductive materials containing organic materials or pastes, e.g. for thick films
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818—Bonding techniques
    • H01L2224/81801—Soldering or alloying
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06517—Bump or bump-like direct electrical connections from device to substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06551—Conductive connections on the side of the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06572—Auxiliary carrier between devices, the carrier having an electrical connection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06579—TAB carriers; beam leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06582—Housing for the assembly, e.g. chip scale package [CSP]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01004—Beryllium [Be]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/0102—Calcium [Ca]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01023—Vanadium [V]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01024—Chromium [Cr]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01047—Silver [Ag]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01049—Indium [In]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/0105—Tin [Sn]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01051—Antimony [Sb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01057—Lanthanum [La]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01068—Erbium [Er]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19043—Component type being a resistor

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Wire Bonding (AREA)
  • Connecting Device With Holders (AREA)

Abstract

一种底部引线的半导体封装件，包括：(a)至少两片以上有多个粘接焊盘的半导体芯片；(b)绝缘电路膜，包括：有多个通孔的绝缘底膜、多条第一金属线、多个突出的导电性内焊盘、多个突出的导电性外焊盘、电互连各芯片同一端子用的多条第二金属线；(c)包括内引线和外引线的引线框架；(d)密封包括所述芯片、绝缘电路膜和引线框架的内引线在内的一定区域的封装壳以及多个凹座，在扩大封装件容量的同时，使之轻薄短小型化。

Description

底部引线的半导体封装件
本发明涉及一种半导体封装件，特别涉及一种引线框架的外引线从封装壳下面露出的底部引线的半导体封装件。
一般来说，以往大部分的半导体封装件是用环氧树脂模压化合物模塑一个半导体芯片而构成的。为提供芯片与外部装置的信号传送通道，引线框架的外引线具有从封装壳外侧突出的形状。
像这样的现有半导体封装件用下列工艺制造：在引线框架的垫片上粘接半导体芯片的小片粘接工艺；用金属布线电气连接垫片上的半导体芯片和引线框架的内引线的金属布线连接工艺；用环氧树脂等密封包括芯片、内引线和金属布线的一定区域，形成封装壳的模压工艺；切断支承引线框架各引线的连接杆，使之成为各自独立的封装件，同时使从封装壳外侧突出外引线形成预定形状的弯折的修整/成形工艺。这样制造出来的半导体封装件，用焊接法将其外引线与印刷电路板的图形一致地装配，以便进行与外部装置的信号输入输出动作。
但是，上述现有的半导体封装件，其结构适于仅内装一片芯片，因而在容量的扩大上有限制。并且，为了在上述结构中内装两个以上的芯片，只能使引线框架的垫片加大，伴随着对封装件小型化的限制，工艺上也要求高难技术。
此外，现有半导体封装件由于必须按国际标准化规格来保持封装壳的大小和管脚排列，因而有时存在不能恰当地满足用户需要的问题。
另一方面，为了解决现有技术产生的外引线突出的突出形封装件的安装问题，提出了所谓的底部引线封装，即，从封装壳下面露出外引线的结构。这也同样，因需要支撑芯片用的垫片和支撑该垫片的连接杆，必须用金属布线连接芯片和引线框架的内引线，在结构上存在浸透水分和金属薄片等可靠性低下的问题，并对封装件尺寸的减小有限制。并且，以往的底部引线封装件，从其构造的观点来看，因必须进行修整、成形、模压、修整顺序的制造工艺，因而在工艺上难以实施应该进行的回火(reflash)和洗涤(scrubbing)。
本发明的目的在于提供一种大容量化且轻薄短小型化的底部引线的半导体封装件。
本发明的另一目的是提供一种组装容易、可靠性高且易满足用户需要的底部引线的半导体封装件。
按照本发明，底部引线的半导体封装件包括：(a)至少两片以上有多个粘接焊盘的半导体芯片；(b)绝缘电路膜，包括：有多个通孔的绝缘底膜；形成于所述底膜上下面上的多条第一金属线；形成于所述各第一金属线上、与所述各半导体芯片的粘接焊盘电气连接的多个突出的导电性内焊盘；形成于所述各第一金属线上、与所述内焊盘相距预定间隔的多个突出的导电性外焊盘；为了电气互连位于所述底膜上下位置上的各芯片同一端子等，形成于所述通孔壁面，与所述内焊盘电连接的多条第二金属线；(c)引线框架，包括所述绝缘电路膜的外焊盘与外部装置电连接用的内引线和外引线；(d)封装壳，密封包括所述半导体芯片、绝缘电路膜和引线框架的内引线在内的一定区域，并包括形成于与所述外部装置传送信号用的电连接位置上的多个凹座，所述外引线从所述凹座引出，与所述封装壳的下面同一平面地露出。
所述绝缘电路膜的构成如下：在聚合物系列的底膜上下面上形成由预定金属层构成的金属线；在该金属线上形成与芯片的粘接焊盘连接的多个内焊盘和与引线框架的内引线连接的多个外焊盘；在贯通所述底膜而形成的贯穿通孔中填充金属，形成连接芯片同一端子的通孔。其中，所述金属线的金属层由选自Cu、Ni、Au或Cu、Ni、Cr、Au或Cu、Ni、Co、Au或导电率为10-8Ω/cm以上的金属中之任意一种所构成，层厚在25.4μm(1mil)内。此外，所述内、外焊盘形成突出的1μm～20μm的高度，5μm×5μm～200μm×200μm的大小，所述通孔的直径为10μm～200μm。
所述引线框架的构造为：具有与绝缘电路膜的外焊盘连接的内引线和用于连接基板的外引线的多根引线用连接杆支撑在侧轨(side rail)内侧，其厚度形成为最小50.8μm(2mil)以上，可使用Cu、MF202、合金42(合金42)、Orin194或合金50(Alloy50)等几乎全部的具有导电性的金属。
所述各向异性导体包括液态和固态的树脂和导电性颗粒，所述树脂使用环氧树脂或变形环氧树脂、聚酯或变形聚合物、丙烯酸树脂或变形酯、硅酮树脂、苯氧基树脂、聚氨酯、聚硫化物、氨基丙烯酸酯、聚补体以及其它可经加热、紫外线、室温而硬化的聚合物等，并包含导电颗粒。其中，所述颗粒由Ag、Ni、In、Sn、氧化铟锡中任意一种或其合金组成，或由导电率为10-8Ω/cm以上的金属构成。恬当的尺寸大小为3μm～5μm，其形状无论球形、四角形、三角形、六面体、四角锥以及三角锥等都可以。
另一方面，本发明提供的底部引线的半导体封装件，在封装壳的下面形成向内陷入的多个凹座。在该凹座上设置与封装壳下面保持同一平面的引线框架的外引线。其中，所述凹座在两侧相互分离地排列成Z字形，两侧的凹座之间保持预定的间隔。这种凹座为大小101.6μm×101.6μm～101.6μm×127μm(4mil×4mil～4mil×5mil)的直角四角形或正方形，其深度为25.4μm(1mil)～400μm。上述两侧的凹座间隔保持在25.4μm(1mil)～5mm，为保持上述间隔，弯折的内引线的弯曲角度为-10°～+10°为好。
像这样的本发明的底部引线的半导体封装件用形成有预定金属图形和连接焊盘的绝缘电路膜作支承芯片和导电用的介质，并在该膜的上下面上直接粘接芯片，因而能最大可能地利用现有的组装工艺，实现至少装载两片以上的芯片的大容量封装件。此外，使用上述绝缘电路膜和各向异性导体，可实现大容量化和轻薄短小型化的封装件。
并且，本发明的底部引线的半导体封装件，去除了引线框架的垫片和连接该垫片的连接杆等，因而能有效地防止因连接杆而产生的通过微小间隙的湿气浸入，可以减少因进行布线连接而产生的模压粘接的不良，用芯片的倒置粘接方式可防止因环氧树脂模塑化合物产生的α粒子所引起的焊缝误差(bead error)等，从而可提高其可靠性。
此外，本发明能够自由设计绝缘电路膜，提供排列管脚的独立性，因而易满足用户的要求。
附图的简要说明如下：
图1是表示本发明一实施例的底部引线的半导体封装件的结构的剖面图。
图2是表示本发明另一实施例的底部引线的半导体封装件的结构的剖面图。
图3A和3B是分别表示本发明的底部引线的半导体封装件的外引线底面的示意图。
图4是本发明底部引线的半导体封装件的重要部分的放大剖面图。
图5A是用于本发明的底部引线的半导体封装件中的绝缘电路膜的局部放大剖面图，图5B是图5A的平面图，图5C是表示通孔构造的放大剖面图。
图6是用于本发明的底部引线的半导体封装件中的引线框架的平面图。
图7是表示本发明的底部引线的半导体封装件的模压后状态的平面图。
下面，参照附图说明本发明的最佳实施例。
参照图1、图2、图3A和3B，半导体芯片1、2以倒置粘接方式粘接在绝缘电路膜3的上下面上，即芯片的上面、亦即电极排列面面面相对。绝缘电路膜3的一侧上连接引线框架的内引线4，形成芯片与外部装置的电信号传送通路。
各半导体芯片1、2和绝缘电路膜3的连接部分，以及绝缘电路膜3与引线框架的内引线4的连接部分之间填充各向异性体5，电连接各连接部分。
此外，用封装壳6密封包括半导体芯片1、2、绝缘电路膜3以及引线框架的内引线4的一定区域。封装壳6的下面形成预定大小的凹座6a，在该凹座6a上设置引线框架的外引线7。
参照图4和图5A～5C，绝缘电路膜3包括聚合物系列的底膜3a，和在其上、下面上由预定金属层形成的金属线3b。如图5B所示，在该金属线3b上形成与芯片1、2的粘接焊盘1a、2a连接的多个内焊盘3c，以及与引线框架内引线4连接的多个外焊盘3d，从而使半导体芯片1、2和引线框架的内引线4分别形成电连接。并且，这样的绝缘电路膜3中，形成有将该绝缘电路膜3上下面上粘连的半导体芯片1、2的同一端子(例如：CAS与CAS，RAS与RAS)电互连的通孔8。如图5c所示，该通孔8的两侧壁面上形成相互电隔离的金属9，连接上述底膜3a上部的内焊盘和上述底膜3a下部的内焊盘。
上述结构的绝缘电路膜3的厚度为25.4μm(1mil)左右，金属线3b的金属层由Cu、Ni、Au或Cu、Ni、Cr、Au或Cu、Ni、Co、Au或有10-8Ω/cm以上的导电率的金属中的任意一种构成。所述内焊盘3c和外焊盘3d从金属线3b表面突出预定高度，该突出的高度在1μm～20μm的范围，其大小为5μm×5μm～200μm×200μm的范围，该通孔8的大小为其直径在10μm～200μm的孔。
参照图6，在引线框架的侧轨S内侧，用连接杆D支承有与绝缘电路膜3的外焊盘3d连接的内引线4和与印刷电路板连接的外引线7的多根引线，构成引线框架。这样的结构去除了以往引线框架的垫片和支承该垫片的连接杆，因而可解决因这些垫片和连接杆产生的可靠性问题和轻薄短小型化的问题。
上述本发明的引线框架的厚度形成在50.8μm(2mil)以上，使用Cu、MF202、合金42、Orin194和合金50中的任意一材料，导电率在10-8Ω/cm以上的金属也可以。
参照图2，在与绝缘电路膜3的外焊盘3d连接的内引线4的部位上涂敷预定金属，以提高其结合力。上述金属可用银、锡、或铟等。
图4所示的各向异性导体5包括液态和固态的树脂和导电颗粒。所述树脂可用环氧树脂或变形环氧树脂、聚酯或变形聚合物、丙烯酸树脂或变形酯、苯氧基树脂、聚氨酯、聚硫化物、氨基丙烯酸酯、聚补体以及其它可经加热、紫外线、室温而硬化的聚合物等。
上述颗粒用Ag、Ni、In、Sn、氧化铟锡中的任意一种或用它们的合金，也可用导电率在10-8Ω/cm以上的金属。所用的颗粒大小为3μm～5μm较好，其形状无论是球形，四角形、三角形、六面体、四角锥、和三角锥等都可以。
参照图3A和3B，在封装壳6的下面，形成陷入其内侧的多个凹座6a，该凹座6a中设置与封装壳下面保持同一平面的外引线7。为使所述外引线7与印刷电路板的粘接作业容易进行，在其端部弯折预定长度，最好使该弯折部分与上述封装壳的下面保持同一平面。上述凹座6a排列在两侧，在两侧相互错开地排列为Z字形，与它相对应的外引线也具有Z字形。此外，凹座6a由大小为101.6μm×101.6μm～101.6μm×127μm(4mil×4mil～4mil×5mil)的直角四角形或正四方形构成，其深度为25.4μm(1mil)～400μm。
如图3B所示，这种凹座6a最好两侧的凹座保持预定间隔并且成Z字形地排列，这时，两侧凹座的间隔为25.4μm (1mil)～5mm为好。
为保持上述间隔，内引线4应弯折预定角度，其弯折角度最好为-10°～+10°。
下面，说明本发明的底部引线的半导体封装件的制造方法和其作用效果。
首先，用普通的PWB(印刷电路板)制作法制备绝缘电路膜3。即，在底膜3a的上下面上涂敷或电镀预定金属层而形成金属线，最后在通孔8上电镀金属，从而制成有多个焊盘和通孔的绝缘电路膜3。
在制备的绝缘电路膜3上涂敷各向异性导体5后，连接引线框架的内引线4和绝缘电路膜3的外焊盘。然后，用倒置方式将第一半导体芯片1粘接在绝缘电路膜3的一侧面上。亦即，将半导体芯片的粘接焊盘与绝缘电路膜3的内焊盘相对地粘接。随后，用普通的敞开式热处理、紫外线照射或热压等方法进行硬化处理工序。第一半导体芯片1的粘接完成后，用同样的方法在绝缘电路膜3的另一侧面上涂敷各向异性导体5，粘连第二半导体芯片2之后，进行固化处理。
在上述工艺完成后，进行普通半导体封装件的组装工艺。即依次进行模压、修整/成形、测试工艺。模压工艺中，使模压金属模的外引线模压区的金属模为Z字形状，为使引线框架的焊接部位在成形时进入模压壳体的内部，还形成预定深度的凹座6a。另外，上述修整工艺为分割连接杆D和侧轨S的工艺。成形工艺是使焊接的外引线7形成于Z字形的模压区域的凹座6a的部位上，使成形的引线的底与模具的底一致。
经过上述诸工艺，方可制造出图1及图2所示的底部引线的半导体封装件。被制造出的封装件将其从封装壳下面露出的引线焊接在印刷电路板上，进行实际安装，即可输出、输入信号。
如上所述，本发明的底部引线的半导体封装件用形成有预定金属图形和连接焊盘的绝缘电路膜作支承芯片和导电用的介质，在该膜的上下面上直接粘接芯片，故能最大可能地利用现有的组装工艺，至少装载两片以上的芯片，以期实现封装件的大容量化。并且，通过使用上述绝缘电路膜和各向异性导体，提供了可实现大容量化和轻薄短小型化的封装件。
尚且，本发明的底部引线的半导体封装件，去除了引线框架的垫片和连接该垫片的连接杆等，因而能有效地防止因连接杆而产生的通过微小间隙的湿气浸入。通过采用倒置方式粘接芯片，能防止因环氧树脂模塑化合物产生的α粒子所引起的焊缝误差(bead error)等，提高其可靠性。
此外，本发明的绝缘电路膜可自由设计，其管脚的排列有独立性，因此本发明容易满足使用者的要求。

Claims (22)

1.一种底部引线的半导体封装件，其特征在于，包括：
(a)至少两个以上的半导体芯片，各芯片上具有多个粘接焊盘；
(b)绝缘电路膜，包括：有多个通孔的绝缘性底膜；形成于所述底膜上下面上的多条第一金属线；形成于所述各第一金属线上、与所述各半导体芯片的粘接焊盘电连接的多个突出的导电性内焊盘；形成于所述各第一金属线上、与所述内焊盘相距预定间隔的多个突出的导电性外焊盘；为了将位于所述底膜上下位置上的各芯片同一端子电气互连，沿所述通孔壁面形成的、与所述内焊盘电气连接的多条第二金属线；
(c)引线框架，包括使所述绝缘电路膜的外焊盘与外部装置电连接用的内引线和外引线；
(d)封装壳，密封包括所述半导体芯片、绝缘电路膜和引线框架的内引线的一定区域，并包括形成与所述外部装置传送信号用的电连接位置上的多个凹座，所述外引线从所述凹座引出，与所述封装壳的下面同一平面地露出。
2.如权利要求1所述的底部引线的半导体封装件，其特征在于，所述第一、第二金属线选自Cu、Ni、Au的合金；Cu、Ni、Cr、Au的合金；Cu、Ni、Co、Au的合金；以及导电率为10-8Ω/cm以上的金属。
3.如权利要求1所述的底部引线的半导体封装件，其特征在于，所述金属线的金属层的厚度在25.4μm以内。
4.如权利要求1所述的底部引线的半导体封装件，其特征在于，所述内焊盘和外焊盘从所述金属层的表面高出1μm～20μm。
5.如权利要求4所述的底部引线的半导体封装件，其特征在于，所述内焊盘和外焊盘的大小为5μm×5μm～200μm×200μm。
6.如权利要求1所述的底部引线的半导体封装件，其特征在于，所述内焊盘和外焊盘的大小为5μm×5μm～200μm×200μm。
7.如权利要求1所述的底部引线的半导体封装件，其特征在于，所述通孔的直径为10μm～200μm。
8.如权利要求1所述的底部引线的半导体封装件，其特征在于，所述引线框架具有下列结构：用连接杆支承包括在侧轨内侧上与绝缘电路膜的外焊盘连接的内引线和与基板连接用的外引线的多根引线。
9.如权利要求8所述的底部引线的半导体封装件，其特征在于，所述引线框架的厚度在50.8μm以上。
10.如权利要求8所述的底部引线的半导体封装件，其特征在于，所述引线框架选自Cu、MF202、合金42、Orin194和合金50中的任意一种。
11.如权利要求1所述的底部引线的半导体封装件，其特征在于，还包括含有树脂和树脂内的导电性颗粒的各向异性导体，该各向异性导体用于固定所述连接部分，同时用所述颗粒使所述粘接焊盘等与所述绝缘电路膜电连接。
12.如权利要求11所述的底部引线的半导体封装件，其特征在于，所述树脂选自液态或固态的下列树脂中的任意一种：环氧树脂或变形环氧树脂、聚酯或变形聚合物、丙烯酸树脂或变形酯、硅酮树脂、苯氧基树脂、聚氨酯、聚硫化物、氨基丙烯酸酯、聚补体以及其它可经加热、紫外线、室温而硬化的聚合物。
13.如权利要求11所述的底部引线的半导体封装件，其特征在于，所述颗粒选自Ag、Ni、In、Sn和氧化铟锡中的一种或一种以上。
14.如权利要求11所述的底部引线的半导体封装件，其特征在于，所述颗粒为导电率在10-8Ω/cm的金属。
15.如权利要求11所述的底部引线的半导体封装件，其特征在于，所述颗粒包括选自球形、四角形、三角形、六面体、四角锥和三角锥中的一种以上的形状，其大小为3μm～15μm。
16.如权利要求1所述的底部引线的半导体封装件，其特征在于，所述外引线从其端部弯折预定的长度，并保持该弯曲的面与所述封装壳下面为同一平面。
17.如权利要求1所述的底部引线的半导体封装件，其特征在于，所述凹座由大小为101.6μm×101.6μm～101.6μm×127μm的直角四角形或正方形构成，其深度为25.4μm～400μm。
18.如权利要求17所述的底部引线的半导体封装件，其特征在于，所述凹座为正方形形状。
19.如权利要求1所述的底部引线的半导体封装件，其特征在于，所述凹座在两侧相互错开地排列，形成Z字形状。
20.如权利要求19所述的底部引线的半导体封装件，其特征在于，所述凹座与所述粘接焊盘的排列相对应地形成两列，所述两列凹座分隔预定间隔。
21.如权利要求20所述的底部引线的半导体封装件，其特征在于，所述间隔为25.4μm～5mm。
22.如权利要求20所述的底部引线的半导体封装件，其特征在于，为保持两列凹座间的分离，内引线弯折预定的角度，其弯折角度为-10°～+10°。
CN97109573A 1996-03-06 1997-03-06 底部引线的半导体封装件 Expired - Fee Related CN1085409C (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR5799/96 1996-03-06
KR1019960005799A KR100192180B1 (ko) 1996-03-06 1996-03-06 멀티-레이어 버텀 리드 패키지

Publications (2)

Publication Number Publication Date
CN1164764A CN1164764A (zh) 1997-11-12
CN1085409C true CN1085409C (zh) 2002-05-22

Family

ID=19452482

Family Applications (1)

Application Number Title Priority Date Filing Date
CN97109573A Expired - Fee Related CN1085409C (zh) 1996-03-06 1997-03-06 底部引线的半导体封装件

Country Status (6)

Country Link
US (1) US5834836A (zh)
JP (1) JP2997744B2 (zh)
KR (1) KR100192180B1 (zh)
CN (1) CN1085409C (zh)
DE (1) DE19709259B4 (zh)
GB (1) GB2310954B (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101578702B (zh) * 2006-10-18 2015-11-25 威世通用半导体公司 具有铝外壳的封装集成电路器件

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5945130A (en) * 1994-11-15 1999-08-31 Vlt Corporation Apparatus for circuit encapsulation
JP3359846B2 (ja) * 1997-07-18 2002-12-24 シャープ株式会社 半導体装置
US6353268B1 (en) 1997-08-22 2002-03-05 Micron Technology, Inc. Semiconductor die attachment method and apparatus
US6646354B2 (en) 1997-08-22 2003-11-11 Micron Technology, Inc. Adhesive composition and methods for use in packaging applications
US5861678A (en) 1997-12-23 1999-01-19 Micron Technology, Inc. Method and system for attaching semiconductor dice to substrates
KR100631910B1 (ko) * 1999-12-13 2006-10-04 삼성전자주식회사 동일한 칩을 사용하는 멀티-칩 패키지
US6828884B2 (en) * 2001-05-09 2004-12-07 Science Applications International Corporation Phase change control devices and circuits for guiding electromagnetic waves employing phase change control devices
JP2003017645A (ja) * 2001-07-03 2003-01-17 Shinko Electric Ind Co Ltd リードフレーム及びその製造方法
US6949818B2 (en) * 2002-12-30 2005-09-27 Dongbu Electronics Co., Inc. Semiconductor package and structure thereof
CN100382263C (zh) * 2004-03-05 2008-04-16 沈育浓 具有多层布线结构的半导体晶片装置及其封装方法
US7947535B2 (en) * 2005-10-22 2011-05-24 Stats Chippac Ltd. Thin package system with external terminals
SG135066A1 (en) 2006-02-20 2007-09-28 Micron Technology Inc Semiconductor device assemblies including face-to-face semiconductor dice, systems including such assemblies, and methods for fabricating such assemblies
US7812430B2 (en) * 2008-03-04 2010-10-12 Powertech Technology Inc. Leadframe and semiconductor package having downset baffle paddles
US20100314730A1 (en) * 2009-06-16 2010-12-16 Broadcom Corporation Stacked hybrid interposer through silicon via (TSV) package
US8120158B2 (en) * 2009-11-10 2012-02-21 Infineon Technologies Ag Laminate electronic device
CN104685621B (zh) * 2012-09-26 2017-05-10 丰田自动车株式会社 电气部件

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0513743A2 (en) * 1991-05-17 1992-11-19 Fujitsu Limited Semiconductor package for surface mounting

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6480032A (en) * 1987-09-21 1989-03-24 Hitachi Maxell Semiconductor device and manufacture thereof
JP2855719B2 (ja) * 1989-03-20 1999-02-10 セイコーエプソン株式会社 半導体装置
JPH0671062B2 (ja) * 1989-08-30 1994-09-07 株式会社東芝 樹脂封止型半導体装置
US5204287A (en) * 1991-06-28 1993-04-20 Texas Instruments Incorporated Integrated circuit device having improved post for surface-mount package
US5438224A (en) * 1992-04-23 1995-08-01 Motorola, Inc. Integrated circuit package having a face-to-face IC chip arrangement
JP2829188B2 (ja) * 1992-04-27 1998-11-25 株式会社東芝 樹脂封止型半導体装置
US5247423A (en) * 1992-05-26 1993-09-21 Motorola, Inc. Stacking three dimensional leadless multi-chip module and method for making the same
US5548087A (en) * 1993-05-07 1996-08-20 At&T Corp. Molded plastic packaging of electronic devices
JP2565091B2 (ja) * 1993-07-01 1996-12-18 日本電気株式会社 半導体装置およびその製造方法
US5413970A (en) * 1993-10-08 1995-05-09 Texas Instruments Incorporated Process for manufacturing a semiconductor package having two rows of interdigitated leads
US5477082A (en) * 1994-01-11 1995-12-19 Exponential Technology, Inc. Bi-planar multi-chip module
KR0149798B1 (ko) * 1994-04-15 1998-10-01 모리시다 요이치 반도체 장치 및 그 제조방법과 리드프레임
US5527740A (en) * 1994-06-28 1996-06-18 Intel Corporation Manufacturing dual sided wire bonded integrated circuit chip packages using offset wire bonds and support block cavities
US5600181A (en) * 1995-05-24 1997-02-04 Lockheed Martin Corporation Hermetically sealed high density multi-chip package
US5677567A (en) * 1996-06-17 1997-10-14 Micron Technology, Inc. Leads between chips assembly

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0513743A2 (en) * 1991-05-17 1992-11-19 Fujitsu Limited Semiconductor package for surface mounting

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101578702B (zh) * 2006-10-18 2015-11-25 威世通用半导体公司 具有铝外壳的封装集成电路器件

Also Published As

Publication number Publication date
CN1164764A (zh) 1997-11-12
JP2997744B2 (ja) 2000-01-11
KR970067809A (ko) 1997-10-13
US5834836A (en) 1998-11-10
DE19709259A1 (de) 1997-11-06
GB9704631D0 (en) 1997-04-23
KR100192180B1 (ko) 1999-06-15
JPH10303365A (ja) 1998-11-13
GB2310954B (en) 2000-09-20
GB2310954A (en) 1997-09-10
DE19709259B4 (de) 2006-02-23

Similar Documents

Publication Publication Date Title
CN1085409C (zh) 底部引线的半导体封装件
CN1065662C (zh) 半导体芯片封装及其制造方法
CN1071491C (zh) 半导体封装件
US6228683B1 (en) High density leaded ball-grid array package
CN1159956C (zh) 装有芯片封装的电路基板的端电极及其制造方法
CN1151554C (zh) 半导体器件、其制造方法以及组合型半导体器件
US6569755B2 (en) Semiconductor device having an improved structure for preventing cracks, improved small sized semiconductor and method of manufacturing the same
US7037756B1 (en) Stacked microelectronic devices and methods of fabricating same
US6064111A (en) Substrate for holding a chip of semi-conductor package, semi-conductor package, and fabrication process of semi-conductor package
CN1124652C (zh) 半导体器件装配构造和半导体器件装配方法
KR100212607B1 (ko) 반도체 칩 팩키지
US20070013038A1 (en) Semiconductor package having pre-plated leads and method of manufacturing the same
CN101752329A (zh) 带有堆积式互联承载板顶端散热的半导体封装及其方法
CN1104742C (zh) 底部引线半导体封装及其制造方法
JPH10294418A (ja) 半導体装置
KR20080015699A (ko) 반도체 장치 및 그 제조 방법
JP3143081B2 (ja) 半導体パッケ−ジ用チップ支持基板、半導体装置及び半導体装置の製造法
KR100437821B1 (ko) 반도체 패키지 및 그 제조방법
TWI228304B (en) Method for manufacturing ball grid package
CN1228838C (zh) 结构强化的开窗型半导体封装件
KR100688596B1 (ko) 몰디드 리드리스 패키지 및 그 제조 방법
JP2000236033A (ja) 半導体装置並びにその製造方法
CN115799075A (zh) 封装框架及其制作方法、封装结构
JPH09246447A (ja) 半導体装置及びその製造方法
JPH1041436A (ja) 半導体パッケージの製造方法

Legal Events

Date Code Title Description
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C06 Publication
PB01 Publication
C14 Grant of patent or utility model
GR01 Patent grant
C17 Cessation of patent right
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20020522

Termination date: 20130306