CN1228838C - 结构强化的开窗型半导体封装件 - Google Patents

结构强化的开窗型半导体封装件 Download PDF

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CN1228838C
CN1228838C CNB021461562A CN02146156A CN1228838C CN 1228838 C CN1228838 C CN 1228838C CN B021461562 A CNB021461562 A CN B021461562A CN 02146156 A CN02146156 A CN 02146156A CN 1228838 C CN1228838 C CN 1228838C
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substrate
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conductivity
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CN1494131A (zh
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蔡宪聪
苏文生
陈坤煌
林进兴
许祐铭
吴文隆
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LIANCE SCIENCE AND TECHNOLOGY Co Ltd
UTAC Taiwan Corp
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    • HELECTRICITY
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    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
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    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
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    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
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    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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    • H01L2224/92Specific sequence of method steps
    • H01L2224/921Connecting a surface with connectors of different types
    • H01L2224/9212Sequential connecting processes
    • H01L2224/92142Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92147Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
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Abstract

一种结构强化的开窗型(Window-Type)半导体封装件,是在一开设有开孔的基板上接置至少一芯片,使芯片的作用表面覆盖住、并部分外露于开孔中,从而形成在开孔中的焊线电性连接至基板;然后,敷设一不具有导电性的材料至芯片上除作用表面外的部位;接着,在基板上形成一上封装胶体以包覆芯片及不具有导电性的材料,并形成一下封装胶体,使下封装胶体填充至基板的开孔中且包覆住焊线。使用不具有导电性的材料,在形成上封装胶体前包覆芯片,能够避免芯片(尤其在经历较大热应力的角落或边缘部位)在后续制程中,如上封装胶体固化或热循环中,产生裂损,确保半导体封装件的品质及可靠性。

Description

结构强化的开窗型半导体封装件
技术领域
本发明是关于一种开窗型半导体封装件,特别是关于一种强化结构的开窗型半导体封装件,它能够增进半导体封装件中的芯片承载件的机械强度(Mechanical Strength)。
背景技术
开窗型半导体封装件是一种先进的封装技术,其特点在于基板开设有至少一贯穿基板的开孔,使芯片以覆盖该开孔的方式接置在基板上,并通过形成于该开孔中的焊线,电性连接至该基板。这种封装结构的优点是能够缩短焊线的长度,因而可有效增进芯片与基板间的电性传递及性能。
现有的开窗型球栅阵列(Window-Type Ball Grid Array,WBGA)半导体封装件1,如图4所示,是使用一基板10,其具有一上表面100及一相对的下表面101,并开设有一贯穿基板10的开孔102。一芯片11是以面朝下(Face-Down)的方式接置在基板10的上表面100上,使芯片11的作用表面110朝向并覆盖开孔102,从而令形成在该作用表面110上的焊垫111外露于该开孔102中。多条焊线12是形成于开孔102中、且焊接至芯片11的焊垫111,使芯片11的作用表面110借焊线12电性连接至基板10的下表面101。然后,一个下封装胶体13以印刷(Printing)方式形成于基板10的下表面101上,并填充至开孔102中,其作用是包覆焊线12。一上封装胶体14以模压(Molding)方式形成于基板10的上表面100上,是用来包覆芯片11。最后,多个焊球15是植接于基板10的下表面101上不影响下封装胶体13的区域,且作为半导体封装件1的输入/输出(Input/Output,I/O)端以电性连接芯片11至外界装置,如印刷电路板上(Printed Circuit Board,未图标)。
然而,由于上封装胶体14(一般使用树脂化合物,如环氧树脂)与芯片11(直接接触上封装胶体14)的热膨胀系数(Coefficient of ThermalExpansion,CTE)不同,在高温环境中,如上封装胶体14固化(Curing)或后续热循环的情况下,尤其在芯片11的角落或边缘部位会承受来自上封装胶体14较大的热应力(Stress)而产生裂损(Crack),且裂损现象可能会蔓延至芯片11的其它部位;对于较长或较大的芯片这种情形会经常发生,有时问题会比较严重,使制成的封装产品的品质及可靠性受损。
发明内容
为克服上述技术的不足,本发明的主要目的在于提供一种结构强化的开窗型半导体封装件,可增进承载于该半导体封装件中的芯片的机械强度,以避免芯片产生裂损。
本发明的一种结构强化的开窗型半导体封装件,包括:一基板,具有一上表面及一相对的下表面,且开设有至少一贯穿该上、下表面的开孔;至少一芯片,具有一作用表面及一相对的非作用表面,该芯片的作用表面接置在该基板的上表面上并覆盖该开孔,使该作用表面上的电性区外露于该基板的开孔中;一不具有导电性的材料,敷设在该芯片上除作用表面外的部位;多条焊线,形成在该基板的开孔中,用来电性连接该芯片的电性区至该基板的下表面;一上封装胶体,形成于该基板的上表面上,用来包覆该芯片及该不具有导电性的材料;一下封装胶体,形成于该基板的下表面上、并填充至该开孔中,用来包覆该焊线;以及多个焊球,植接于该基板的下表面上不影响该下封装胶体的区域。
上述半导体封装件具有诸多优点。使用的不具有导电性的材料,在形成上封装胶体前包覆芯片,即可增进芯片的机械强度,也可为芯片提供一缓冲区域,以应对后续热应力的作用;因此,在高温环境中,如上封装胶体固化或后续热循环的情况下,能够避免经强化的芯片(尤其在经历较大热应力的角落或边缘部位)产生裂损,从而确保芯片结构的完整,进而提高半导体封装件的品质及可靠性。
附图说明
为让本发明的上述及其它目的、特征以及优点能更明显易懂,下面与较佳实施例配合附图,详细说明本发明的实施例,附图的内容简述如下:
图1A至图1E是本发明的实施例1的半导体封装件的制造过程示意图;
图2是本发明的实施例2的半导体封装件的剖视图;
图3是本发明的实施例3的半导体封装件的剖视图;以及
图4是一现有半导体封装件的剖视图。
具体实施方式
以下配合附图1A至图1E、图2及图3详细说明本发明的结构强化的开窗型半导体封装件的实施例。
实施例1
图1A至图1E显示本发明实施例1的半导体封装件2的制程步骤。
如图1A所示,首先,制备一基板片(Substrate Plate)20,其是由多条基板21整合而成,相邻基板21以图中虚线分界。各基板21具有一上表面210及一相对的下表面21,并开设有至少一贯穿上表面210、、下表面211的开孔212。基板片20主要由现树脂材料制成,如环氧树脂(Epoxy Resin)、聚酰亚胺(Polyimide)、BT(Bismaleimide Triazine)树脂、FR-4树脂等。
如图1B所示,接置至少一芯片22在各基板21的上表面210上。芯片22是由具有一布设有多个电子器件及电路(未图标)以及焊垫221的作用表面220及一相对的非作用表面222所构成,使芯片22的作用表面220粘设在对应的基板21的上表面210上、并覆盖开孔212,使得形成在作用表面220上的焊垫221外露在开孔212中。
接着,还如图1B(图1B的下半部是其上半部的上视图)所示,敷设一不具有导电性的材料23,至芯片22上除作用表面220外的部位,使不具有导电性的材料23完全覆盖各基板21上所接置的芯片22,但不能覆盖作用表面220。该不具有导电性的材料最好是选择具有弹性的材料。
不具有导电性的材料23可以采用模板印刷(Stencil-Printing)的方式敷设,就是使用一现有模板(未图标),选择性地将不具有导电性的材料23印刷在芯片22上。由于模板印刷技术属于现有技术,这里不再重复说明。再有,现有点胶(Dispensing)技术也可用于敷设不具有导电性的材料23。
然后,如图1C所示,进行一焊线(Wire-Bonding)作业,在各基板21的开孔212中形成多条焊线24,例如金线。其中,焊线24是将芯片22的作用表面220上的焊垫221焊接至对应的基板21的下表面211,使芯片22通过焊线24电性连接至基板21。
或者,不具有导电性的材料23也可在焊线制程完成后再敷设,换言之,在芯片22接置于各基板21上并形成供电性连接的焊线24后,再敷设不具有导电性的材料23至芯片22上。不具有导电性的材料23的敷设在后续用以包覆焊线24的印刷制程前进行较好。
接着,进行一印刷作业以在各基板21的下表面211上形成一下封装胶体25,使下封装胶体25填充至对应的基板21的开孔212、并包覆对应的焊线24。由于印刷技术属于现有技术,在此不再重复说明。
如图1D所示,进行一模压作业,在基板21的上表面210上形成一上封装胶体26,使上封装胶体26包覆住所有芯片22及不具有导电性的材料23。上封装胶体25可以由现有树脂化合物,如环氧树脂制成。
或者,也可使不具有导电性的材料23的顶部外露出上封装胶体26,因而降低上封装胶体26的厚度以缩减整体结构尺寸。
然后,进行一植球(Ball-Implantation)作业以植接多个焊球27在各基板21的下表面211上不影响下封装胶体25的区域。焊球27的高度H大于下封装胶体25突出基板21的下表面211的厚度T,即H>T。焊球27可作为输出/输入(Input/Output,I/O)端,以电性连接芯片22至外界装置,如印刷电路板(Printed Circuit Board,未图标)。
最后,如图1E所示,进行一切单(Singulation)作业,沿图1D所示的虚线切割上封装胶体26与基板片20,使各基板21分离、形成多条半导体封装件2。
上述半导体封装件2具有诸多优点。使用不具有导电性的材料23(该材料具有一定的弹性),在形成上封装胶体26前包覆芯片22,能够增进芯片22的机械强度,并且为芯片22提供了缓冲区域,以应对后续热应力的作用。因此,在高温环境中,如上封装胶体26固化或后续热循环的情况下,能够避免强化的芯片22(尤其在经历较大热应力的角落或边缘部位)产生裂损,从而能确保芯片22的结构完整,提高半导体封装件2的品质及可靠性。
实施例2
图2显示本发明的实施例2的半导体封装件2′。如图所示,此半导体封装件2′与上述半导体封装件2的结构相似,故相同组件以相同于实施例1的标号表示。
半导体封装件2′与上述半导体封装件2的不同之处在于,芯片22的非作用表面222没有用不具有导电性的材料23包覆而外露,因此,不具有导电性的材料23仅遮覆住芯片22的侧面223,而没有包覆作用与非作用表面220、222,但它充分地覆盖了芯片22的角落或边缘部位。芯片22的非作用表面222外露使不具有导电性的材料23的厚度降低,因而可缩减整体封装结构尺寸,并由于减少不具有导电性的材料23的用量,从而降低半导体封装件2′的生产成本。
实施例3
图3显示本发明的实施例3的半导体封装件2″。
此半导体封装件2″与上述实施例2的半导体封装件2′的不同之处在于,芯片22的非作用表面222是进一步外露出上封装胶体26,因此,芯片22的非作用表面222没有用不具有导电性的材料23或上封装胶体26包覆,而直接与大气接触,有助于释放芯片22运作时产生的热量,故可有效增进半导体封装件2″的散热效率。再有,芯片22的非作用表面222的外露,使上封装胶体26的厚度降低,因而可缩减整体封装结构尺寸。

Claims (12)

1.一种结构强化的开窗型半导体封装件,其特征在于,该半导体封装件包括:
一基板,具有一上表面及一相对的下表面,且开设有至少一贯穿该上、下表面的开孔;
至少一芯片,具有一作用表面及一相对的非作用表面,该芯片的作用表面接置在该基板的上表面上、并覆盖该开孔,使该作用表面上的电性区域外露于该基板的开孔中;
一不具有导电性的材料,敷设在该芯片上除作用表面外的部位,且该不具有导电性的材料具有弹性;
多条焊线,形成于该基板的开孔中,用来电性连接该芯片的电性区域至该基板的下表面;
一上封装胶体,形成在该基板的上表面上,用来包覆该芯片及该不具有导电性的材料;以及
一下封装胶体,形成在该基板的下表面上、并填充至该开孔中,用以包覆该焊线。
2.如权利要求1所述的半导体封装件,其特征在于,它还包括:多条焊球,植接在该基板的下表面上不影响该下封装胶体的区域。
3.如权利要求1所述的半导体封装件,其特征在于,该不具有导电性的材料完全覆盖住该芯片上除作用表面外的部位。
4.如权利要求1所述的半导体封装件,其特征在于,该不具有导电性的材料的顶部外露出该上封装胶体。
5.如权利要求1所述的半导体封装件,其特征在于,该芯片的非作用表面外露出该不具有导电性的材料。
6.如权利要求1所述的半导体封装件,其特征在于,该芯片的非作用表面外露出该上封装胶体。
7.如权利要求1所述的半导体封装件,其特征在于,该不具有导电性材料以印刷方式敷设。
8.如权利要求1所述的半导体封装件,其特征在于,该不具有导电性材料以点胶方式敷设。
9.如权利要求1所述的半导体封装件,其特征在于,该芯片的电性区域上形成有多条焊垫,使该焊垫与该焊线焊接。
10.如权利要求1所述的半导体封装件,其特征在于,该上封装胶体以模压方式制成。
11.如权利要求1所述的半导体封装件,其特征在于,该下封装胶体以印刷方式制成。
12.如权利要求2所述的半导体封装件,其特征在于,该焊球的高度大于该下封装胶体突出该基板下表面的厚度。
CNB021461562A 2002-10-30 2002-10-30 结构强化的开窗型半导体封装件 Expired - Fee Related CN1228838C (zh)

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