CN1071491C - 半导体封装件 - Google Patents

半导体封装件 Download PDF

Info

Publication number
CN1071491C
CN1071491C CN97109574A CN97109574A CN1071491C CN 1071491 C CN1071491 C CN 1071491C CN 97109574 A CN97109574 A CN 97109574A CN 97109574 A CN97109574 A CN 97109574A CN 1071491 C CN1071491 C CN 1071491C
Authority
CN
China
Prior art keywords
semiconductor package
package part
lead
metal
insulator chain
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
CN97109574A
Other languages
English (en)
Other versions
CN1164765A (zh
Inventor
朴桂灿
卢吉燮
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
SK Hynix Inc
Original Assignee
Hyundai Electronics Industries Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hyundai Electronics Industries Co Ltd filed Critical Hyundai Electronics Industries Co Ltd
Publication of CN1164765A publication Critical patent/CN1164765A/zh
Application granted granted Critical
Publication of CN1071491C publication Critical patent/CN1071491C/zh
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495Lead-frames or other flat leads
    • H01L23/49575Assemblies of semiconductor devices on lead frames
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/563Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001Core members of the connector
    • H01L2224/45099Material
    • H01L2224/451Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001Core members of the connector
    • H01L2224/45099Material
    • H01L2224/451Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45117Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/45124Aluminium (Al) as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001Core members of the connector
    • H01L2224/45099Material
    • H01L2224/451Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144Gold (Au) as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73203Bump and layer connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73203Bump and layer connectors
    • H01L2224/73204Bump and layer connectors the bump connector being embedded into the layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • H01L24/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • H01L24/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/00014Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/0102Calcium [Ca]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01068Erbium [Er]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01078Platinum [Pt]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01079Gold [Au]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/12Passive devices, e.g. 2 terminal devices
    • H01L2924/1204Optical Diode
    • H01L2924/12044OLED
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Wire Bonding (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

一种半导体封装件,包括:通过形成有导电用的金属图形的绝缘电路膜设置至少两个以上的半导体芯片,使芯片面面相对地粘接;在绝缘电路膜的两侧连接引线框架的内引线构成与芯片外部电连接的通路;绝缘电路膜包括绝缘性的底膜和导电用金属线;金属线上形成有与半导体芯片的粘接焊盘连接的多个内焊盘和与引线框架的内引线相连的多个外焊盘;为电气互连底膜上下的特定金属线而形成多个通孔,以期在扩大容量的同时,实现封装件的轻薄短小型化。

Description

半导体封装件
本发明涉及一种半导体封装件,特别涉及一种既扩大容量又具有轻、薄、短、小型化的多芯片封装件。
以往,一般认为塑性半导体封装件是用环氧树脂模压化合物等树脂模塑一个半导体芯片构成的,并且利用具有用于安装于基板上的外引线的、称为引线框架的部件构成信号传送体系。
图1为依据现有技术用树脂进行半导体封装件封装的剖面图。
参照图1,标号1为半导体芯片,2为在支承半导体芯片1的同时、用作外部电信号传送路径的引线框架,3为将引线框架2的内引线2a与半导体芯片1进行电连接的金属引线,4分别为芯片1、引线框架2的内引线2a和金属引线3的密封壳。
如图所示,半导体芯片1通过粘接剂被粘接并被固定在引线框架2的垫片2c上,半导体芯片1与引线框架2的内引线2a通过金属引线3而电连接。用塑性树脂密封这样形成的包括半导体芯片1、引线框架2的内引线2a和金属引线3的一定区域,形成大致呈长方形的封装壳,即封装壳4。并且,在封装壳4的两侧保持一定间隔地突出形成用于向基板安装的外引线2b。
像这样的现有半导体塑封装件通过下列工艺制造:在引线框架2的垫片2c上粘接半导体芯片1的小片粘接工艺;用金属引线3电连接垫片2c上的半导体芯片1和引线框架2的内引线2a的金属布线连接工艺;密封包括芯片1、内引线2a和金属引线3的一定区域,形成封装壳4的模压工艺;切断支承引线框架2的各引线的连接杆等(图中未示出),在各自独立的封装件上相互分开,同时在封装壳4两侧形成预定弯曲形状的、突出的外引线2b的修整/成形工艺。这样制造出来的半导体封装件,通过软熔发亮处理将外引线2b与基板的图形一致地装配,以便起到输入、输出电信号等作用。
但是,如上所述,现有的普通半导体封装件存在这样的问题;即在芯片对封装件尺寸的占有率上有限制,难以实现大容量的封装件。
还有,现有的单个塑封件,用金属布线连接方法将用作芯片与外部电通路的铝或金等金属引线焊接在引线框架或基板上,因而存在因引线可靠性等问题而导致的质量低劣的问题。
并且,为实现大容量,在一个封装壳中内装两个以上的芯片而构成多级封装件时,现有结构的半导体封装件因引线回路高度在封装件的轻、薄、短、小型化方面受到限制。在两个芯片对置构成时,一个芯片必须使用设计不同的镜像芯片(mirror chip),从而在制造工艺上产生问题。另外,现有半导体封装件,在设计导电用内引线和多芯片组件时,管脚排列结构的自由度受到限制,还存在难与用户管脚对应的问题。
本发明的目的在于提供一种能够实现大容量化和轻薄短小型化的半导体封装件。
本发明的半导体封装件包括:(a)至少两个以上的半导体芯片,各芯片上有多个粘接焊盘;(b)绝缘电路膜,包括:有多个通孔的绝缘性底膜;形成于所述底膜上、下面上的多条第一金属线;形成于所述各第一金属线上、与所述各半导体芯片的粘接焊盘电连接的多个突出的导电性内焊盘;形成于所述各第一金属线上、与所述内焊盘相距预定间隔的多个突出的导电性外焊盘;为电气互连各芯片的同一端子而置于所述底膜上、下位置、沿所述通孔的壁面形成的、与所述各芯片的内焊盘电连接的多条第二金属线;(c)引线框架,包括将所述绝缘电路膜的外焊盘与外部装置电连接用的内引线;
其中,各半导体芯片按其上面相对的方式粘接在所述绝缘电路膜上。
此外,本发明中,由于绝缘电路膜上的内焊盘和外焊盘从金属线表面突出预定高度地形成,故半导体芯片和引线框架的内引线可电连接,用包含颗粒的各向异性导体可粘接绝缘电路膜、半导体芯片,以及引线框架的内引线。此时,所述绝缘电路膜的厚度为10μm~100μm,内焊盘和外焊盘高为1μm~20μm、大小为5μm×5μm~200μm×200μm。并且,与绝缘电路膜的外焊盘连接的引线框架的内引线上涂敷有导电率为10-8Ω/cm以上的金属,如Ag、Sn或In等。再者,各向异性导体是包括液态和固态的树脂,是选自:环氧树脂或变形环氧树脂、聚酯或变形聚合物、丙烯酸树脂或变形酯、硅酮树脂、苯氧基树脂、聚氨酯、聚硫化物、氨基丙烯酸酯、聚补体(alexin)以及其它经加热、紫外线、室温而硬化的聚合物等中的树脂。各向异性导体中所含的颗粒,其大小为3μm~15μm,由Ag、Ni、In、Sn、铟锡氧化物或它们的合金构成,或由导电率为10-8Ω/cm的金属构成,其形状可为球形、四角形、三角形、六面体、四角锥和三角锥等。
另外,本发明中,可与金属线同一平面地形成绝缘电路膜上的内、外焊盘;在半导体芯片的粘接焊盘上形成预定高度的金属粘接剂,以与绝缘电路膜电连接;通过包含颗粒的各向异性导体粘接绝缘电路膜与半导体芯片;绝缘电路膜的外焊盘和引线框架的内引线用热压粘接。
粘接剂的高度为5μm~20μm,宽度为30μm~200μm,由金、焊料、传导性聚合物等具有导电性的金属和聚合物组成。
另一方面,构成绝缘电路膜的金属线包括Cu、Ni、Au或Cu、Ni、Cr、Au或Cu、Ni、Co、Au,形成为1mil以内。通孔的直径为10μm~200μm。
按照本发明的封装件,利用上述结构的绝缘电路膜,将两个芯片面对面地粘接而形成,因而具有不必使用镜像芯片,用同样设计的芯片就可构成的效果。
此外,还有下列效果:因绝缘电路膜取代了现有的引线框架的小片粘接和金属布线粘接,因而可提高可靠性,可自由地排列引线框架的管脚。
并且,由于省略了布线粘接工艺,可提高可靠性,又由于以芯片面对面的方式进行粘接,可防止由环氧树脂模塑化合物而产生的α颗粒的影响。
再者,本发明还具有下列优点:可实现既大容量又有多层结构的轻薄短小型化的封装件,易满足用户的需求。
附图的简要说明如下:
图1是表示现有技术的普通半导体封装件结构的剖面图。
图2是表示本发明第一实施例的半导体封装件的整体结构的剖面图。
图3是表示图2所示半导体封装件中的芯片、绝缘电路膜以及引线框架的连接关系的详细示意图。
图4A是图3所示半导体封装件中所使用的绝缘电路膜结构的部分平面图,图4B是沿图4A中A-A线剖切的剖面图,图4C是沿图4A的B-B线剖切的剖面图。
图5是表示本发明第二实施例的半导体封装件的整体结构的剖面图。
图6是表示图5所示半导体封装件中,芯片、绝缘电路膜以及引线框架的连接关系的详细的示意图。
图7A~7C是图6所示半导体封装件中使用的绝缘电路膜结构的部分剖面图、部分平面图和表示通孔的剖面放大图。
图8是表示芯片、绝缘电路膜以及引线框架之间连接关系的其它结构的剖面图。
图9是表示本发明第三实施例的剖面图。
下面,参照附图说明本发明的最佳实施例。
图2是展示本发明第一实施例的半导体封装件的整体构造的剖视图,图3详细示出图2所示半导体封装件中,芯片、绝缘电路膜和引线框架间的连接关系,图4A是表示图3所示半导体封装件中所使用的绝缘电路膜的构造的部分平面图,图4B是沿图4A的A-A线切断的剖面图,图4C是沿图4A的B-B线切断的剖面图。
附图中,参考标号10和10'指半导体芯片,20指绝缘电路膜,31指内引线,32指外引线,40指各向异性导体,50指封装件壳。
参照图2和图3,半导体芯片10、10'粘在绝缘电路膜20的上、下面上,粘接面与芯片的上面即排列电极的面相对。绝缘电路膜20中,形成导电用的金属图形,绝缘电路膜20的两侧连接引线框架的内引线31,构成与芯片外部电连接的通路。
用各向异性导体40粘接半导体芯片10、10'、绝缘电路膜20以及内引线31,用封装壳50密封包括半导体芯片10和10'、绝缘电路膜20和内引线31的一定区域,在封装壳50的下面,从内引线31延伸形成的外引线32露出,安装在基板(图中未示出)上。
亦即,为实现高可靠性,本发明将芯片直接粘接在弹性绝缘电路膜上,将该绝缘电路膜的端点与引线框架的内引线粘接。不仅如此,为了大幅度增加芯片对封装件的占有率,使限定容量能至少扩大两倍以上,在除去引线框架的垫片后,在绝缘电路膜的两面上安装芯片。
按照一般制作弹性电路板的方法,或稍加变更,即可制作绝缘电路膜20。下面参照图4A~4C具体进行描述。
参照图4A~4C,在底膜21大致中间的上下面上,涂敷或电镀预定厚度的Cu、Ni和Au,形成金属线22,其厚度为10μm至200μm左右,从而构成本发明用的绝缘电路膜20。其中,最好是所述底膜21厚度为25μm,在其上依序涂敷或电镀的镍和金属的厚度为0.3μm和0.1~0.15μm。
金属线22上,从其表面突出预定高度地形成与半导体芯片10、10'的粘接焊盘连接用的多个内焊盘23,和与引线框架的内引线31连接的多个外焊盘24。上述焊盘23、24的突出高度最好在1μm~20μm范围内,大小最好为5μm×5μm~200μm×200μm。并且,在所述金属线22上形成互连上下粘着的半导体芯片10、10'同一端子的通孔25,例如互连芯片的CAS(列地址选通)端子、互连RAS(行地址选通)端子等。该通孔25中,沿其内壁面的预定部分分别形成预定的传导金属26,以电连接上下芯片。该实施例中,上述通孔25的大小在直径10μm~200μm的范围内。按相对的两个内焊盘23共用的方式形成上述通孔25。
另一方面,图中示出由Cu、Ni、Au构成金属线22的实例,但并不限于此,也可由Cu、Ni、Cr、Au或Cu、Ni、Co、Au构成,还可由其导电率在10-8Ω/cm以上的金属等构成。
为使上述结构的绝缘电路膜20与半导体芯片10、10'以及使绝缘电路膜20与内引线31粘接而涂敷的各向异性导体40包括树脂和导电用的预定颗粒。该树脂为液态或固态,例如为环氧树脂或变形环氧树脂、聚酯或变形聚合物、丙烯酸树脂或变形酯、硅酮树脂、苯氧基树脂、聚氨酯、聚硫化物、氨基丙烯酸酯、聚补体(polgalexins)及其它由于加热、紫外线、室温而硬化的聚合物等多种形式。并且,含在上述树脂中的颗粒为由银、金、镍、铟、锡、铟锡氧化物等单独的金属或合金构成,也可由导电率为10-8Ω/cm以上的金属构成,该颗粒大小为3μm~15μm。
另一方面,与上述绝缘电路膜20的外焊盘连接的引线框架的内引线31上,涂敷银、锡、铟或导电率大于10-8Ω/cm的金属,可提高其导电性。
下面,对上述本发明的半导体封装件的制造方法及其作用效果进行说明。
首先,绝缘电路膜20的制造方法与制造普通印制电路板(PCB)的方法相似。具体地说,在形成多个通孔25的底膜21的上、下面上涂敷预定厚度的Cu和电镀预定厚度的Ni、Au之后,进行构图,形成金属线22、内焊盘23和外焊盘24,然后,进行金属电镀,形成穿过通孔25的传导金属线26,从而制成有多个焊盘的绝缘电路膜。此时,绝缘电路膜20上的焊盘、即与芯片的粘接焊盘和引线框架的内引线粘连的上下面上的内焊盘23和外焊盘24,比周边的金属线22的高度高约5μm以上。
将这样制作的绝缘电路膜与无垫片的引线框架同时置于粘接机之后,用各向异性导体粘接半导体芯片和内引线。这时,使用液态各向异性导体时,用分散槽或丝网印刷法涂敷各异性导体,然后用加热或紫外线硬化的方法粘接。若为固态的各向异性导体时,则用加热和压力进行粘接。
用上述方法粘接一个芯片之后,用相同的方法对相对侧面上的芯片进行粘接。
上述工艺结束后,进行与普通半导体封装件的制造工艺相同的模压、修整和成形等工艺,制成图示的半导体封装件。
另一方面,图5~7示出本发明半导体封装件的第二实施例,下面对此进行说明。
图5是本发明第二实施例的半导体封装件的整体结构的剖视图,图6是表示在图5所示半导体封装件中,芯片、绝缘电路膜以及引线框架的连接关系的详细示意图,图7A~7C分别是表示图6所示半导体封装件所使用的绝缘电路膜的结构的部分剖面图、部分平面图和表示通孔的剖面放大图。图中,与上述实施例相同的部分用相同的符号表示。
如图所示,本发明的该实施例的结构与上述第一实施例的构造大体相同,但用形成于芯片粘接焊盘上的金属粘接剂60连接绝缘电路膜20和半导体芯片10、10'来构成。再者,半导体芯片10、10'和绝缘电路膜20用各向异性导体40连接,而引线框架的内引线31和绝缘电路膜20的外焊盘没用各向异性导体40支承,采用其它粘接。
换言之,本发明的该实施例,形成于绝缘电路膜20的金属线22上的内、外焊盘不从表面上突出,而是与表面为同一平面地构成。另一方面,芯片的粘接焊盘上形成预定高度的金属粘接剂60,用各向异性导体40粘接半导体芯片10、10'和绝缘电路膜20来构成,并且绝缘电路膜20与引线框架的内引线31不是用各向异性导体40的方法,而是用合金结合来构成的。此外,与图4A的实施例不同,通孔25与各内焊盘23一一对应地形成。
这种结构中,上述金属粘接剂60的高度为5μm~20μm,宽度为30μm~200μm。并且,上述金属粘接剂60由主要成分为金、焊料、传导性聚合物等所有具有导电性的金属以及聚合物等构成。
用与第一实施例大体相同的工艺制造上述结构的该实施例。只是在制作绝缘电路膜20之后,首先用热压法将上述绝缘电路膜20的外焊盘与引线框架的内引线合金结合,然后将其放在适当的工作台上,用各向异性导体将半导体芯片10粘接于绝缘电路膜20上。此后,经硬化,粘接相对侧面的半导体芯片10'后,进行普通封装装配工艺中的后部工艺,制成图5所示的半导体封装件。
像这样按本发明第二实施例制作的半导体封装件的作用效果与上述第一实施例相同,故省略。
图8是本发明第三实施例的示意图,仅示出其中重要部分。
如图所示,半导体芯片10、10'与绝缘电路膜20通过绝缘电路膜20上的焊盘和芯片上的金属粘接剂连接。其它结构与上述第二实施例的结构相同,作用效果也与该第二实施例相同,因而这里省略其详细说明。
图9A和9B是本发明第三实施例的示意图,它们示出不同的引线框架的外引线。亦即,上述封装件中,其外引线从封装壳的下面露出,而本实施例的封装件中,基板安装用的外引线从封装壳的两外侧突出,形成预定的弯曲形状。图示实施例中,仅示出两种外引线的形状,外引线可具有其它多种结构。其它部分的构成及其作用效果与上述实施例相同。
这样制作的本发明的半导体封装件,与普通半导体封装件相同,将向封装壳外部突出外露的外引线焊在基板上而装配,起输入、输出电信号的作用。并且由于实现了大容量且轻薄短小型化,所以能提高安装率。
按照上述详细说明,本发明的半导体封装件利用绝缘电路膜,该绝缘电路膜形成有上下芯片电气导通用的金属图形和同样的端子互连用的通孔,将两个芯片以面面相对的方式粘接而构成,构成既大容量又轻薄短小的封装件,不必使用镜像芯片,就能够取得易满足用户要求的效果。
再者,本发明的半导体封装件,用上述绝缘电路膜代替现有的引线框架的小片粘接和金属布线粘接,因而可提高可靠性,并可自由地排列引线框架的管脚。通过采用芯片的面面相对的方式,可防止因环氧树脂模型化合物而产生的α颗粒。

Claims (28)

1.一种半导体封装件,其特征在于包括:
(a)至少两个以上的半导体芯片,各芯片具有多个粘接焊盘;
(b)绝缘电路膜,包括有多个通孔的绝缘性的底膜;形成于所述底膜上下面上的多条第一金属线;形成于所述各第一金属线上、与所述各半导体芯片的粘接焊盘电连接的多个突出的导电性内焊盘;形成于所述各第一金属线上、与所述内焊盘相距预定间隔的多个突出的导电性外焊盘;位于所述底膜上下位置、电气互连各芯片的同一端子用的、沿所述通孔的壁面形成的、与所述各芯片的内焊盘电连接的多条第二金属线;
(c)包括将所述绝缘电路膜的外焊盘与外部装置电连接用的内引线的引线框架;
其中,各半导体芯片按其面面相对的方式粘接在所述绝缘电路膜上。
2.如权利要求1所述的半导体封装件,其特征在于,还包括密封壳,它将包括所述半导体芯片、绝缘电路膜及引线框架的内引线的一定区域密封包装。
3.如权利要求2所述的半导体封装件,其特征在于,在所述封装壳的两外侧突出地形成与印刷电路板电连接用的引线框架的外引线。
4.如权利要求2所述的半导体封装件,其特征在于,在所述封装壳的下面外露地构成与印刷电路板电连接用的引线框架的外引线。
5.如权利要求1所述的半导体封装件,其特征在于,用包括树脂和颗粒的各向异性电导体粘接所述绝缘电路膜、半导体芯片的焊盘以及引线框架的内引线。
6.如权利要求5所述的半导体封装件,其特征在于,所述绝缘电路膜的厚度为10μm~200μm,内焊盘和外焊盘具有1μm~20μm的高度,5μm×5μm~200μm×200μm的大小。
7.如权利要求5所述的半导体封装件,其特征在于,在与所述绝缘电路膜的外焊盘连接的引线框架的内引线上,涂敷选自导电率为10-8Ω/cm以上的金属中的一种金属。
8.如权利要求7所述的半导体封装件,其特征在于,所述金属为Ag、Sn或In。
9、如权利要求5所述的半导体封装件,其特征在于,所述树脂选自液态或固态的下列材料:环氧树脂或变形环氧树脂、聚酯或变形聚合物、丙烯酸树脂或变形酯、硅酮树脂、苯氧基树脂、聚氨酯、聚硫化物、氨基丙烯酸酯、聚补体以及其它经加热、紫外线、室温而硬化的聚合物。
10.如权利要求5所述的半导体封装件,其特征在于,所述颗粒的大小为3μm~15μm。
11.如权利要求10所述的半导体封装件,其特征在于,所述颗粒选自Ag、Ni、In、Sn、氧化铟锡中的任意一种或由其中的两种以上组成的合金。
12.如权利要求10所述的半导体封装件,其特征在于,所述颗粒由导电率为10-8Ω/cm以上的金属组成。
13.如权利要求5所述的半导体封装件,其特征在于,所述颗粒的形状包括球形、四角形、三角形、六面体、四角锥和三角锥等。
14.如权利要求1所述的半导体封装件,其特征在于,所述第一金属线由Cu、Ni、Au或Cu、Ni、Cr、Au、或Cu、Ni、Co、Au构成,其厚度在24.5μm以内。
15.如权利要求1所述的半导体封装件,其特征在于,所述通孔的直径形成为10μm~200μm。
16.根据权利要求1所述的半导体封装件,其特征在于,在所述半导体芯片的焊盘上形成有具有预定高度的导电粘接剂,并且该半导体封装件包括具有树脂和导电颗粒的各向异性导体,以通过所述颗粒使所述导电粘接剂与所述绝缘电路膜电连接。
17.如权利要求16所述的半导体封装件,其特征在于,所述粘接剂的高为5μm~20μm,宽为30μm~200μm。
18.如权利要求16所述的半导体封装件,其特征在于,所述粘接剂用金、焊料、传导性聚合物等所有具有导电性的金属构成。
19.如权利要求16所述的半导体封装件,其特征在于,所述绝缘电路膜的厚度为10μm~200μm。
20.如权利要求16所述的半导体封装件,其特征在于,所述内引线上涂敷选自导电率为10-8Ω/cm的金属中的一种金属。
21.如权利要求20所述的半导体封装件,其特征在于,所述金属为Ag、Sn或In。
22.如权利要求16所述的半导体封装件,其特征在于,所述树脂选自液态或固态的下列材料:环氧树脂或变形环氧树脂、聚酯或变形聚合物、丙烯酸树脂或变形酯、硅酮树脂、苯氧基树脂、聚氨酯、聚硫化物、氨基丙烯酸酯、聚补体以及其它经加热、紫外线、室温而硬化的聚合物。
23.如权利要求16所述的半导体封装件,其特征在于,所述颗粒的大小为3μm~15μm。
24.如权利要求23所述的半导体封装件,其特征在于,所述颗粒选自Ag、Ni、In、Sn、氧化铟锡中的任意一种或由其中的两种以上组成的合金。
25.如权利要求23所述的半导体封装件,其特征在于,所述颗粒由导电率为10-8Ω/cm以上的金属组成。
26.如权利要求16所述的半导体封装件,其特征在于,所述颗粒的形状包括球形、四角形、三角形、六面体、四角锥和三角锥等。
27.如权利要求1所述的半导体封装件,其特征在于,所述第一金属线由Cu、Ni、Au或Cu、Ni、Cr、Au或Cu、Ni、Co、Au构成,其厚度在24.5μm以内。
28.如权利要求1所述的半导体封装件,其特征在于,所述通孔的直径为10μm~200μm。
CN97109574A 1996-03-06 1997-03-06 半导体封装件 Expired - Fee Related CN1071491C (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
KR1019960005798A KR100192179B1 (ko) 1996-03-06 1996-03-06 반도체 패키지
KR5798/1996 1996-03-06
KR5798/96 1996-03-06

Publications (2)

Publication Number Publication Date
CN1164765A CN1164765A (zh) 1997-11-12
CN1071491C true CN1071491C (zh) 2001-09-19

Family

ID=19452481

Family Applications (1)

Application Number Title Priority Date Filing Date
CN97109574A Expired - Fee Related CN1071491C (zh) 1996-03-06 1997-03-06 半导体封装件

Country Status (7)

Country Link
US (1) US6080931A (zh)
JP (1) JP2858246B2 (zh)
KR (1) KR100192179B1 (zh)
CN (1) CN1071491C (zh)
DE (1) DE19709295B4 (zh)
GB (1) GB2310953B (zh)
TW (1) TW358230B (zh)

Families Citing this family (39)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR19990060952A (ko) * 1997-12-31 1999-07-26 김영환 반도체 패키지
US6159765A (en) * 1998-03-06 2000-12-12 Microchip Technology, Incorporated Integrated circuit package having interchip bonding and method therefor
US6147411A (en) * 1998-03-31 2000-11-14 Micron Technology, Inc. Vertical surface mount package utilizing a back-to-back semiconductor device module
KR100304959B1 (ko) 1998-10-21 2001-09-24 김영환 칩 적층형 반도체 패키지 및 그 제조방법
SG85103A1 (en) * 1999-01-28 2001-12-19 United Microelectronics Corp Multi-chip chip scale package
JP2000340737A (ja) * 1999-05-31 2000-12-08 Mitsubishi Electric Corp 半導体パッケージとその実装体
JP2001007280A (ja) * 1999-06-24 2001-01-12 Mitsubishi Electric Corp 半導体装置およびその実装構造
KR100333384B1 (ko) * 1999-06-28 2002-04-18 박종섭 칩 사이즈 스택 패키지 및 그의 제조방법
WO2001026155A1 (fr) * 1999-10-01 2001-04-12 Seiko Epson Corporation Dispositif a semi-conducteur, procede et dispositif permettant d'obtenir ce dernier, carte de circuit imprime et equipement electronique
KR20010036142A (ko) * 1999-10-06 2001-05-07 윤종용 다층 리드를 갖는 반도체 칩 패키지
KR100650049B1 (ko) * 2000-01-06 2006-11-27 삼성전자주식회사 멀티 칩 패키지를 이용하는 적층 패키지
TW455964B (en) * 2000-07-18 2001-09-21 Siliconware Precision Industries Co Ltd Multi-chip module package structure with stacked chips
JP4447143B2 (ja) * 2000-10-11 2010-04-07 新光電気工業株式会社 半導体装置及びその製造方法
JP4051893B2 (ja) * 2001-04-18 2008-02-27 株式会社日立製作所 電子機器
US6828884B2 (en) * 2001-05-09 2004-12-07 Science Applications International Corporation Phase change control devices and circuits for guiding electromagnetic waves employing phase change control devices
DE10138278C1 (de) * 2001-08-10 2003-04-03 Infineon Technologies Ag Elektronisches Bauteil mit aufeinander gestapelten elektronischen Bauelementen und Verfahren zur Herstellung derselben
JP2003318360A (ja) * 2002-04-19 2003-11-07 Hitachi Ltd 半導体装置およびその製造方法
KR100460062B1 (ko) * 2002-04-23 2004-12-04 주식회사 하이닉스반도체 멀티 칩 패키지 및 그 제조 방법
KR20030095778A (ko) * 2002-06-14 2003-12-24 삼성전자주식회사 회로형 메탈층을 이용한 적층형 반도체 패키지 및 그제조방법
JP3838178B2 (ja) * 2002-08-29 2006-10-25 ソニー株式会社 半導体装置
KR100484088B1 (ko) * 2002-12-06 2005-04-20 삼성전자주식회사 멀티 칩 패키지용 다이 어태치와 경화 인라인 장치
US6949818B2 (en) * 2002-12-30 2005-09-27 Dongbu Electronics Co., Inc. Semiconductor package and structure thereof
US7217995B2 (en) * 2004-11-12 2007-05-15 Macronix International Co., Ltd. Apparatus for stacking electrical components using insulated and interconnecting via
CN100365814C (zh) * 2004-12-16 2008-01-30 南通富士通微电子股份有限公司 背对背封装集成电路及其生产方法
US7208843B2 (en) * 2005-02-01 2007-04-24 Avago Technologies General Ip (Singapore) Pte. Ltd. Routing design to minimize electromigration damage to solder bumps
US20070130759A1 (en) * 2005-06-15 2007-06-14 Gem Services, Inc. Semiconductor device package leadframe formed from multiple metal layers
US7439100B2 (en) * 2005-08-18 2008-10-21 Semiconductor Components Industries, L.L.C. Encapsulated chip scale package having flip-chip on lead frame structure and method
JP5065586B2 (ja) * 2005-10-18 2012-11-07 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
US7511371B2 (en) * 2005-11-01 2009-03-31 Sandisk Corporation Multiple die integrated circuit package
CN101371353B (zh) * 2006-01-25 2011-06-22 日本电气株式会社 电子装置封装体、模块以及电子装置
SG135066A1 (en) 2006-02-20 2007-09-28 Micron Technology Inc Semiconductor device assemblies including face-to-face semiconductor dice, systems including such assemblies, and methods for fabricating such assemblies
US20080157307A1 (en) * 2006-12-28 2008-07-03 Semiconductor Manufacturing International (Shanghai) Corporation Lead frame
JP5405785B2 (ja) * 2008-09-19 2014-02-05 ルネサスエレクトロニクス株式会社 半導体装置
TWI490988B (zh) * 2012-03-21 2015-07-01 Chipmos Technologies Inc 半導體封裝結構
US9627948B2 (en) * 2014-04-11 2017-04-18 Remy Technologies Llc Electric machine with combined insulator and terminal assembly
CN106876287A (zh) * 2017-02-21 2017-06-20 深圳市江波龙科技有限公司 一种sip封装方法及一种sip模组
CN108376677B (zh) * 2018-03-12 2020-04-21 成都海威华芯科技有限公司 一种对侧级联半导体芯片装置及级联方法
CN114121845A (zh) * 2020-09-01 2022-03-01 Jmj韩国株式会社 半导体封装
KR102341396B1 (ko) * 2021-05-04 2021-12-21 제엠제코(주) 반도체 패키지 및 이에 적용되는 금속 브릿지

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5331235A (en) * 1991-06-01 1994-07-19 Goldstar Electron Co., Ltd. Multi-chip semiconductor package

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4949224A (en) * 1985-09-20 1990-08-14 Sharp Kabushiki Kaisha Structure for mounting a semiconductor device
US5438224A (en) * 1992-04-23 1995-08-01 Motorola, Inc. Integrated circuit package having a face-to-face IC chip arrangement
US5247423A (en) * 1992-05-26 1993-09-21 Motorola, Inc. Stacking three dimensional leadless multi-chip module and method for making the same
US5548087A (en) * 1993-05-07 1996-08-20 At&T Corp. Molded plastic packaging of electronic devices
US5477082A (en) * 1994-01-11 1995-12-19 Exponential Technology, Inc. Bi-planar multi-chip module
KR0149798B1 (ko) * 1994-04-15 1998-10-01 모리시다 요이치 반도체 장치 및 그 제조방법과 리드프레임
US5468995A (en) * 1994-07-05 1995-11-21 Motorola, Inc. Semiconductor device having compliant columnar electrical connections

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5331235A (en) * 1991-06-01 1994-07-19 Goldstar Electron Co., Ltd. Multi-chip semiconductor package

Also Published As

Publication number Publication date
GB2310953A (en) 1997-09-10
GB9704629D0 (en) 1997-04-23
KR970067790A (ko) 1997-10-13
TW358230B (en) 1999-05-11
GB2310953B (en) 2001-01-03
US6080931A (en) 2000-06-27
DE19709295A1 (de) 1997-10-30
DE19709295B4 (de) 2006-05-04
KR100192179B1 (ko) 1999-06-15
JPH1074888A (ja) 1998-03-17
CN1164765A (zh) 1997-11-12
JP2858246B2 (ja) 1999-02-17

Similar Documents

Publication Publication Date Title
CN1071491C (zh) 半导体封装件
CN1188906C (zh) 层叠芯片封装件的制造方法
CN1159956C (zh) 装有芯片封装的电路基板的端电极及其制造方法
US6228683B1 (en) High density leaded ball-grid array package
CN1041254C (zh) 三维结构的半导体器件
US7037756B1 (en) Stacked microelectronic devices and methods of fabricating same
US20070013038A1 (en) Semiconductor package having pre-plated leads and method of manufacturing the same
US5901050A (en) Wired base plate and package for electronic parts
CN100397963C (zh) 电子电路装置及其制造方法
CN1124652C (zh) 半导体器件装配构造和半导体器件装配方法
CN100426496C (zh) 半导体器件及其制造方法
CN1199927A (zh) 封装集成电路元件及其制造方法
TW584972B (en) Optical device module and method of fabrication
CN1199253C (zh) 树脂密封型半导体器件及液晶显示组件
CN1340859A (zh) 芯片型半导体器件
CN1085409C (zh) 底部引线的半导体封装件
CN1104742C (zh) 底部引线半导体封装及其制造方法
CN1679179A (zh) 表面安装型发光二极管
CN103367265B (zh) 多层半导体装置、印刷电路板和多层半导体装置制造方法
CN1134839C (zh) 引线框架及涂敷引线框架的方法
GB2151834A (en) Liquid crystal display device
CN1076873C (zh) 集成芯片的封装及其所使用的连接部件
KR19990069438A (ko) 칩 스택 패키지
US6424541B1 (en) Electronic device attachment methods and apparatus for forming an assembly
JP3162068B2 (ja) 半導体チップの実装方法

Legal Events

Date Code Title Description
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C06 Publication
PB01 Publication
C14 Grant of patent or utility model
GR01 Patent grant
C17 Cessation of patent right
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20010919

Termination date: 20130306