CN1754255A - 直接在无外壳的器件上产生单端固定的接触结构 - Google Patents
直接在无外壳的器件上产生单端固定的接触结构 Download PDFInfo
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- CN1754255A CN1754255A CNA2004800052104A CN200480005210A CN1754255A CN 1754255 A CN1754255 A CN 1754255A CN A2004800052104 A CNA2004800052104 A CN A2004800052104A CN 200480005210 A CN200480005210 A CN 200480005210A CN 1754255 A CN1754255 A CN 1754255A
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- 239000004020 conductor Substances 0.000 claims abstract description 58
- 239000000463 material Substances 0.000 claims abstract description 11
- 238000000576 coating method Methods 0.000 claims description 164
- 239000011248 coating agent Substances 0.000 claims description 163
- 239000011810 insulating material Substances 0.000 claims description 92
- 238000000034 method Methods 0.000 claims description 49
- 239000004065 semiconductor Substances 0.000 claims description 15
- 239000004033 plastic Substances 0.000 claims description 14
- 229920003023 plastic Polymers 0.000 claims description 14
- 230000008569 process Effects 0.000 claims description 13
- 238000001259 photo etching Methods 0.000 claims description 8
- 238000007654 immersion Methods 0.000 claims description 7
- 239000004809 Teflon Substances 0.000 claims description 6
- 229920006362 Teflon® Polymers 0.000 claims description 6
- 238000005266 casting Methods 0.000 claims description 5
- 230000003068 static effect Effects 0.000 claims description 5
- 239000004642 Polyimide Substances 0.000 claims description 4
- 238000000137 annealing Methods 0.000 claims description 4
- 238000009792 diffusion process Methods 0.000 claims description 4
- 238000000608 laser ablation Methods 0.000 claims description 4
- 229920001721 polyimide Polymers 0.000 claims description 4
- 238000007639 printing Methods 0.000 claims description 4
- 238000007650 screen-printing Methods 0.000 claims description 4
- 238000004528 spin coating Methods 0.000 claims description 4
- 239000004593 Epoxy Substances 0.000 claims description 3
- 238000009713 electroplating Methods 0.000 claims description 2
- 150000008442 polyphenolic compounds Chemical class 0.000 claims description 2
- 235000013824 polyphenols Nutrition 0.000 claims description 2
- 239000005001 laminate film Substances 0.000 claims 2
- 239000004698 Polyethylene Substances 0.000 claims 1
- 125000003368 amide group Chemical group 0.000 claims 1
- 125000000468 ketone group Chemical group 0.000 claims 1
- 229920000570 polyether Polymers 0.000 claims 1
- -1 polyethylene Polymers 0.000 claims 1
- 229920000573 polyethylene Polymers 0.000 claims 1
- 239000010408 film Substances 0.000 description 22
- 239000010410 layer Substances 0.000 description 19
- 229910052802 copper Inorganic materials 0.000 description 13
- 239000010949 copper Substances 0.000 description 13
- 229910052751 metal Inorganic materials 0.000 description 13
- 239000002184 metal Substances 0.000 description 13
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 12
- 238000005516 engineering process Methods 0.000 description 10
- 238000005476 soldering Methods 0.000 description 9
- 230000006872 improvement Effects 0.000 description 8
- 238000009413 insulation Methods 0.000 description 7
- 229920002120 photoresistant polymer Polymers 0.000 description 7
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 6
- 230000002349 favourable effect Effects 0.000 description 6
- 239000000758 substrate Substances 0.000 description 6
- 239000010936 titanium Substances 0.000 description 6
- 229910052719 titanium Inorganic materials 0.000 description 6
- 238000000151 deposition Methods 0.000 description 5
- 230000008021 deposition Effects 0.000 description 5
- 230000006698 induction Effects 0.000 description 5
- 230000008719 thickening Effects 0.000 description 5
- 230000008901 benefit Effects 0.000 description 4
- 238000005253 cladding Methods 0.000 description 4
- 238000005260 corrosion Methods 0.000 description 4
- 230000007797 corrosion Effects 0.000 description 4
- 230000007246 mechanism Effects 0.000 description 4
- 230000004888 barrier function Effects 0.000 description 3
- 238000004140 cleaning Methods 0.000 description 3
- 238000010276 construction Methods 0.000 description 3
- 239000012212 insulator Substances 0.000 description 3
- 238000002161 passivation Methods 0.000 description 3
- 239000002985 plastic film Substances 0.000 description 3
- 229920006255 plastic film Polymers 0.000 description 3
- 229920000642 polymer Polymers 0.000 description 3
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- 239000000853 adhesive Substances 0.000 description 2
- 230000001070 adhesive effect Effects 0.000 description 2
- 238000001962 electrophoresis Methods 0.000 description 2
- 238000001704 evaporation Methods 0.000 description 2
- 230000008020 evaporation Effects 0.000 description 2
- 239000007791 liquid phase Substances 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- 229920001643 poly(ether ketone) Polymers 0.000 description 2
- 239000010409 thin film Substances 0.000 description 2
- 206010034972 Photosensitivity reaction Diseases 0.000 description 1
- 238000004026 adhesive bonding Methods 0.000 description 1
- 239000012790 adhesive layer Substances 0.000 description 1
- 239000004411 aluminium Substances 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 230000002180 anti-stress Effects 0.000 description 1
- 229910052787 antimony Inorganic materials 0.000 description 1
- WATWJIUSRGPENY-UHFFFAOYSA-N antimony atom Chemical compound [Sb] WATWJIUSRGPENY-UHFFFAOYSA-N 0.000 description 1
- 239000007767 bonding agent Substances 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 230000000536 complexating effect Effects 0.000 description 1
- 238000001816 cooling Methods 0.000 description 1
- 150000001879 copper Chemical class 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 238000001035 drying Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000000839 emulsion Substances 0.000 description 1
- 239000003292 glue Substances 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- MSNOMDLPLDYDME-UHFFFAOYSA-N gold nickel Chemical compound [Ni].[Au] MSNOMDLPLDYDME-UHFFFAOYSA-N 0.000 description 1
- 230000036039 immunity Effects 0.000 description 1
- 238000003475 lamination Methods 0.000 description 1
- 238000011068 loading method Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 239000003960 organic solvent Substances 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 239000012071 phase Substances 0.000 description 1
- 230000036211 photosensitivity Effects 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 230000008092 positive effect Effects 0.000 description 1
- 238000003825 pressing Methods 0.000 description 1
- 238000003672 processing method Methods 0.000 description 1
- 239000011241 protective layer Substances 0.000 description 1
- 238000004080 punching Methods 0.000 description 1
- 230000003252 repetitive effect Effects 0.000 description 1
- 230000000717 retained effect Effects 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 238000007493 shaping process Methods 0.000 description 1
- 239000002904 solvent Substances 0.000 description 1
- 239000007921 spray Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 229920001169 thermoplastic Polymers 0.000 description 1
- 229920001187 thermosetting polymer Polymers 0.000 description 1
- 239000004416 thermosoftening plastic Substances 0.000 description 1
- MAKDTFFYCIMFQP-UHFFFAOYSA-N titanium tungsten Chemical compound [Ti].[W] MAKDTFFYCIMFQP-UHFFFAOYSA-N 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
- 238000003466 welding Methods 0.000 description 1
- 238000007704 wet chemistry method Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
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- H—ELECTRICITY
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
- H01L23/4822—Beam leads
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- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/568—Temporary substrate used as encapsulation process aid
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
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- H01L2224/2401—Structure
- H01L2224/2402—Laminated, e.g. MCM-L type
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- H01L2224/2405—Shape
- H01L2224/24051—Conformal with the semiconductor or solid-state device
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- H01L2224/241—Disposition
- H01L2224/24151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/24221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/24225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/24226—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the HDI interconnect connecting to the same level of the item at which the semiconductor or solid-state body is mounted, e.g. the item being planar
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- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
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- H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
- H01L2224/241—Disposition
- H01L2224/24151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/24221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/24225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/24227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the HDI interconnect not connecting to the same level of the item at which the semiconductor or solid-state body is mounted, e.g. the semiconductor or solid-state body being mounted in a cavity or on a protrusion of the item
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- H01L2224/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
- H01L2224/82001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI] involving a temporary auxiliary member not forming part of the bonding apparatus
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- H01L2924/01005—Boron [B]
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- H01L2924/01006—Carbon [C]
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- H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
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- H—ELECTRICITY
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- H01L2924/151—Die mounting substrate
- H01L2924/15165—Monolayer substrate
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- H01L2924/1901—Structure
- H01L2924/1904—Component type
- H01L2924/19043—Component type being a resistor
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
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Abstract
通过将一个绝缘材料的覆层和一个导电材料的覆层涂覆到器件以及一个载体上并再与载体分离,直接在一个无外壳的器件上产生一个单端固定的接触结构。
Description
为了从无外壳的电子器件的接线片得到较大的、可钎焊的接触元件已知利用一个导线框架。在此要被接通的器件安置在一个大多金属的冲压的接触载体、即所谓的导线框架上并且器件的接线片通过接触载体的单个引线通过导线粘接电连接。
另一用于使无外壳的器件接触的方法是使用所谓的带自动粘接(TAB)技术。在此柔性的结构通过紧密的可钎焊的内触点和另一可钎焊的外触点构成,即所谓的三脚架。要被接通的器件的接线片与内触点连接。所述外触点用于与电路载体接通。
由此提出本发明的目的是,提出一种用于使无外壳的器件接通的经济的替代方法,它尤其也适用于功率器件。
这个目的通过在独立权利要求中给出的发明得以实现。有利的改进方案由从属权利要求中给出。
本发明的构思是,首先在一个载体上实现单端固定的、平面的导体结构和/或绝缘结构然后使该结构与载体分离。
因此在一个用于加工一个具有接触结构的器件的方法中,将一个电绝缘材料的覆层涂覆到器件和一个设置在器件和/或器件周围的载体上。在此所述载体尤其不必整个面被电绝缘材料的覆层覆盖。所述器件的电接触面在涂覆电绝缘材料的覆层时空着和/或在涂覆电绝缘材料的覆层之后外露。然后在下一步骤中使一个导电材料的覆层涂覆到电绝缘材料的覆层和器件的电接触面上。最后使电绝缘材料的覆层与载体分离。
当然在本发明的范围内对于具有接触面的多个器件、对于具有多个器件的模块和/或对于具有多个接触面的器件都可以相应实现上述方法。
所述导电材料的覆层也可以附加地涂覆到载体的一个不被电绝缘材料的覆层覆盖的部位上。最后将除电绝缘材料的覆层以外的导电材料的覆层与载体分离。
在用于加工一个具有接触结构的器件的方法中,也可以替代地或附加地将一个电绝缘材料的覆层涂覆到器件上。在涂覆电绝缘材料的覆层时使所述器件的一个电接触面空着和/或在涂覆电绝缘材料的覆层之后保持外露。在另一步骤中将一个导电材料的覆层涂覆到电绝缘材料的覆层、器件的电接触面和一个设置在器件上和/或器件周围的载体上。在此所述载体尤其不必整个表面地被导电材料的覆层覆盖。最后将导电材料的覆层与载体分离。
通过所述绝缘材料的覆层和导电材料的覆层在器件上构成一个导体/绝缘体结构形式的平面的单端固定的接触结构。
然后,为了钝化和防潮可以将器件和覆层至少局部地加装外壳和/或通过一个遮盖层覆盖。为此例如将器件、电绝缘材料的覆层和/或导电材料的覆层尤其相互浇铸。这一点例如可以以一个滴状钝化(顶盖)的形式或一个框架浇铸(silgel)的形式实现。但是代替滴状钝化或顶模也可以设想层合另一薄膜。也可以替代地或附加地对于一个塑料薄膜或一个顶盖形式的塑料遮盖层使用一个镍/金保护层。
所述载体最好至少局部地具有一个微小的表面粘附层。该载体尤其是特富龙覆层和/或由特富龙制成。
所述载体也可以具有一个用于器件的支座和/或一个分离导电材料的覆层和/或电绝缘材料的覆层的推出器。
通过露出器件的接触面在电绝缘材料的覆层中开着和/或打开一个在尺寸上大于器件侧面和/或表面60%、尤其是大于80%的窗口,该窗口在器件表面上开着和/或打开。因此本方法特别适用于功率器件,对于该器件在与一个平面导体接触时以相应的尺寸提供一个接触窗口和一个接触面。所述窗口尤其在最大的和/或背离载体的器件表面上打开并最好具有一个大于50毫米2、尤其是大于70毫米2甚至大于100毫米2的绝对尺寸。
也可以选择或附加地为了露出器件的接触面也可以使电绝缘材料的覆层同时这样涂覆,通过打开一个大于器件侧面和/或表面尺寸60%、尤其是大于80%的窗口,在该表面上打开窗口,使器件的接触面至少局部地露出。
另一方面,为了保证更干净地遮盖器件棱边,该窗口的尺寸不大于器件侧面和/或表面尺寸的99.9%,尤其是不大于99%并且优选不大于95%,在该表面上打开窗口。
通过使器件设置在载体上和/或周围,使载体和器件构成一个表面轮廓。所述电绝缘材料的覆层尤其这样涂覆到载体和器件上,使电绝缘材料的覆层衔接在由载体和器件构成的表面轮廓上,即,电绝缘材料的覆层对应于由载体和器件构成的表面轮廓在表面轮廓上延伸。而如果按照现有技术逻辑芯片被嵌入一个聚合物里面,则只是聚合物覆层的底面、而不是聚合物覆层本身衔接表面轮廓。
通过使电绝缘材料的覆层衔接在由载体和器件构成的表面轮廓上,尤其是在一个功率器件作为器件使用的时候,得到两个优点。一方面,保证在背离载体的器件棱边上一个足够厚度的电绝缘材料的覆层,因此避免在高电压或高场强时击穿。另一方面,使电绝缘材料的覆层除了通常非常大的功率器件以外不是这样厚,由此毫无问题地保证以后可能需要的在一个衬底的导体带上的接触面的外露和接触,在该衬底上以后要设置该器件。
所述电绝缘材料的覆层在载体上直线延伸的部位上的厚度与其在器件上直线延伸部位上的厚度的差别小于50%,尤其是小于20%。在基本相同的部位上的厚度差别最好小于5%甚至小于1%。百分比基数尤其以覆层在器件上在其直线延伸部位上的厚度为基准,因此该厚度为100%。在直线延伸的部位上进行比较,因为覆层在载体和器件的内棱边上通常较厚,而在背离载体的器件棱边上通常较薄。
所述电绝缘材料的覆层尤其是由塑料制成。根据继续加工的需要它可以是光敏的或非光敏的。
该覆层通过一个或多个后面的工作步骤实现涂覆:帘铸,浸入、尤其是单面浸入,电晕、尤其是静电电晕、印刷、尤其是丝网印刷,顶模,扩散,旋涂,层合一个薄膜。
所述电绝缘材料的覆层不是薄膜有时是有利的。而当作为电绝缘材料的覆层使用一个薄膜时,则层合在一个真空挤压机中进行是有利的。对此可以设想真空深拉、液压真空挤压、真空压力挤压或类似的层合工艺。压力以有利的方式均匀地施加。层合例如在温度为100℃至250℃、压力为1巴至10巴的条件下进行。层合的准确参数、如压力、温度、时间等可能取决于器件和载体的拓扑结构、薄膜的塑料材料和薄膜的厚度。
所述薄膜可以由任意的热塑塑料、热固塑料和其混合物制成。作为薄膜在按照本发明的方法中优选且以有利的方式使用一个由聚酰亚胺(PI)基、聚乙烯胺(PE)基、多酚基、多醚酮(PEEK)基和/或环氧基的塑料制成的薄膜。在此该薄膜为了改善粘附可以在表面上具有一个粘接层。同样所述衬底表面可以通过一个粘附剂、最好是银锑混合物覆层。
在层合后进行一个退火步骤。通过温度处理和络合改善表面上薄膜的热学的、物理的和机械的粘附特性。
为了涂覆导电材料的覆层、即为了表面接触对导电材料的覆层进行物理的或化学的沉积是有利的。这些物理的方法是溅射和蒸镀(Physical Vapor Deposion PVD)。化学的沉积可以通过气相(Chemical Vapor Deposion,CVD)和/或液相(Liquid Phase ChemicalVapor Deposion,CVD)实现。也可以设想,附加地通过一种上述的方法涂覆一个薄的、例如钛/铜导电分覆层,在其上电镀地沉积一个较厚的例如铜导电分覆层。
在此所述电绝缘材料的覆层这样构成,可以越过一个直到1000微米的高度差。该高度差可能由于载体和设置在载体上和/或周围的半导体芯片的拓扑结构而引起。
在另一改进方案中频繁地重复涂覆,直到电绝缘材料的覆层达到一个确定的厚度。例如将较薄厚度的电绝缘材料分覆层加工成较厚厚度的电绝缘材料的覆层。这些电绝缘材料分覆层优选由一种塑料材料制成。在此也可以设想,使该电绝缘材料分覆层由多种不同的塑料材料制成。它产生一个由分覆层构成的电绝缘材料的覆层。
所述器件的电接触面可以在涂覆电绝缘材料的覆层时空着和/或以后外露。当电绝缘材料的覆层以一个薄膜的形式涂覆时,能够特别有利地在涂覆时就已经实现完全或局部地空着。因此能够从一开始就使用一个具有一个或多个相应开孔或窗口的薄膜,它们例如可以事先通过经济地冲裁或裁切实现。
在一个特殊的改进方案中为了露出器件的电接触面在电绝缘材料的覆层中通过激光烧蚀打开一个窗口。为此所使用的激光器波长在0.1微米至11微米之间。激光器功率在1瓦至100瓦之间。最好使用一个波长为9.24微米的CO2激光器。在此窗口的打开不损害一个可能位于电绝缘材料的覆层下面的由铝、金或铜构成的芯片触点。
在另一改进方案中使用一个光敏的电绝缘材料的覆层并且为了露出器件的电接触面通过一个光刻工艺打开一个窗口。该光刻工艺包括一个光敏的电绝缘材料的覆层的曝光和显影并由此去除电绝缘材料的覆层的已曝光或未曝光的位置。
在打开窗口以后必要时进行一个清洗步骤,其中去除残余的电绝缘材料的覆层。清洗步骤例如湿法化学地实现。尤其也可以设想等离子清洗工艺。
在另一改进方案中使用一个由多个上下设置的不同厚度的导电材料分覆层构成的覆层。例如上下涂覆不同的金属层。分覆层或金属层的数量尤其为2至5层。通过由多个分覆层构成的导电覆层可以组合成一个起到扩散势垒作用的分覆层。这种分覆层例如由一个钛钨合金(TiW)制成。在一个多层结构中以有利的方式直接在要被接触的表面上涂覆一个促进或改进粘附的分覆层。一种这样的分覆层例如由钛制成。
在一个特殊的改进方案中在平面接触之后在导电材料的覆层中和/或在导电材料的覆层上产生至少一个导体带。该导体带可以涂覆到覆层上。尤其是为了产生导体带使覆层形成结构。这意味着,所述导体带在这个覆层中产生。该导体带用于例如一个半导体芯片的电接触。
所述结构一般在一个光刻工艺中实现。为此在导电覆层上涂覆一种光刻胶,干燥并接着曝光和显影。可能衔接一个退火步骤,用于使已涂覆的光刻胶相对于下面的处理工艺稳定。作为光刻胶一般考虑正的和负的感光剂(覆层材料)。光刻胶的涂覆例如通过一个电晕或浸入工艺实现。同样可以设想电镀(静电或电泳的沉积)。
代替一种光刻胶也可以通过一个或多个衔接的工作步骤涂覆其它的可以形成结构的材料:帘铸、浸入、尤其是单面浸入、电晕、尤其是静电电晕、印刷、尤其是丝网印刷、顶模、扩散、纺涂、层合一个薄膜。
为了形成结构也可以使用光敏薄膜,它们被层合并与涂覆光刻胶层类似地进行曝光和显影。
为了产生导体带例如可以如下进行:在一个第一分步骤中使导电覆层形成结构并在接着的分步骤中在产生的导体带上涂覆另一金属层。通过另一金属层使导体带加厚。例如在通过形成结构产生的导体带上电镀地沉积一个厚度从1微米至400微米的铜。然后分离光刻胶层或层合的薄膜或可选使用的可形成结构的材料。这一点例如通过一种有机溶剂、一种碱性显影剂或类似溶剂实现。通过接着的区别腐蚀再去掉平面的、未被金属层加厚的金属导电覆层。由此产生加厚的导体带。
在一个特殊的改进方案中为了加工一个多层的装置多次地执行步骤层合、外露、接触和产生导体带。
通过本发明以有利的方式提供一个新型的工艺用于使设置在半导体芯片、尤其是设置在功率半导体芯片上的接线片或接线接触面电接触和布线。在按照本发明的方法中扁平的连接和特殊的绝缘体还实现一个低感应的连接,用于实现快速且无损失的接通。
通过涂覆电绝缘材料的覆层加工一个电绝缘层。通过按照本发明的涂覆电绝缘材料的覆层加工绝缘层具有下列优点:
-在高温下使用。一个电绝缘材料的覆层在适当地选择材料时耐温可达300℃。
-微少的工艺费用。
-通过使用厚的绝缘层实现高的绝缘场强。
-高产量,例如可以实现有效的工艺过程。
-均匀的绝缘特性,因为通过在真空中加工电绝缘材料的覆层防止夹杂空气。
-可以利用整个芯片接触面,因此可以传导大电流。
-通过平面的接触可以均匀地控制芯片。
-对于一个接触面的接触感应由于有利的平面形状小于在粗导线粘接时的接触感应。
-使接触在振动负荷和机械的冲击负荷下具有高可靠性。
-与竞争的方法相比由于微小的热机械应力具有更高的抗交变负荷能力。
-可以接触到更多的布线面。
-所述的平面连接工艺需要更小的结构高度。实现一个紧凑的结构。
-在多层连接平面中可以实现大面积的用于屏蔽的金属层。这尤其对于电路的EMV(电磁兼容性)特性(寄生发射、抗扰度)具有非常积极的作用。
由本方法的优选改进方案给出本装置的优选和有利的改进方案。
借助于附图由下面的实施例描述给出本发明的其它特征和优点。
附图中:
图1为一种用于在一个功率半导体上产生一个接触结构的方法;
图2为一个可选的器件具有单端固定的接触结构,而该器件还设置在载体周围;
图3以截面图示出按照图2的器件具有单端固定的接触结构,在器件与载体分离并钎焊到其确定位置上以后;
图4以俯视图图示出按照图2的器件具有单端固定的接触结构,在器件与载体分离并钎焊到其确定位置上以后;
图5为另一可选的器件具有单端固定的接触结构,而该器件还设置在一个载体上;
图6为按照图5的器件具有单端固定的接触结构,在器件与载体分离以后;
图7还是一个可选的器件具有单端固定的接触结构,而该器件为了加工设置在一个载体上;
图8为按照图7的器件具有单端固定的接触结构,在器件与载体分离以后。
在图1中可以看出一个特富龙载体1,在其上设置一个半导体芯片形式的器件2。
在半导体芯片2的上表面上存在一个具有一个背离半导体芯片2的接触面210的触点。
如果该半导体芯片2例如是一个晶体管,则该接触面是一个集电极或漏极触点或一个发射极或源极触点的接触面。
配有半导体芯片2的载体1的整个上表面通过载体1的上表面本身并通过半导体芯片2的外露表面给出,该外露表面由这个芯片2的上表面和侧表面确定。
在配有半导体芯片2的载体1的整个表面上在步骤301中在真空条件下涂覆一个电绝缘塑料材料的覆层3,因此这个电绝缘材料的覆层3通过接触面紧密顶靠地覆盖配有半导体芯片2的载体1的表面并粘附在这个表面上。电绝缘材料的覆层3在此衔接在通过外露的载体表面部分并通过半导体芯片2的外露表面给出的表面轮廓上,芯片的表面通过这个芯片2的上表面和侧表面确定。
在步骤301中电绝缘材料的覆层的涂覆最好通过一个或多个衔接的工作步骤实现:帘铸、浸入、尤其是单面浸入、电晕、尤其是静电电晕,印刷、尤其是丝网印刷、顶模、扩散、旋涂。
电绝缘材料的覆层3也可以特别好地通过层合一个薄膜涂覆,尤其是一个聚酰亚胺基或环氧基的塑料材料薄膜。为了改善粘附可以接着进行退火步骤。
电绝缘材料的覆层3作为绝缘体并作为继续涂覆的导电材料的覆层4的载体。
电绝缘材料的覆层3的典型厚度在25-150微米,其中较厚的覆层可以由较薄的电绝缘材料分覆层的层序实现。由此可以以有利的方式实现几十千伏/毫米范围的绝缘场强。
现在在步骤302中通过在电绝缘材料的覆层3中打开一个窗口31露出器件的要被接触的接触面210。此外通过在电绝缘材料的覆层3中打开一个窗口31露出载体1的部位。
用于接触的器件接触面210而打开的窗口的尺寸大于器件尺寸的60%,最好大于80%。
最好通过激光烧蚀在电绝缘材料的覆层3中打开一个窗口31。
然后在步骤303中使器件的外露接触面210和载体1上的每个外露部位与一个导电材料、最好是金属覆层4平面接触,通过使外露的接触面和载体1的外露部位通过常见的工艺金属化并形成结构并因此平面地接触。
例如导电材料的覆层4可以整个平面地不仅涂覆到每个接触面上而且涂覆到背离载体1表面的电绝缘材料的覆层3的上表面上,然后例如通过光刻这样形成结构,使每个接触面保持平面接触并产生在接触面210、载体1的外露部位和电绝缘材料的覆层3上延伸的导体带4,6。
为此最好进行下面的工艺步骤(半添加结构):
i)溅射一个约100纳米厚的钛粘附层和一个约200纳米厚的铜导电层4(步骤303)。
ii)在使用厚胶层或光刻膜5的情况下光刻(步骤304)。
iii)通过一个更厚的导电层6电镀地加厚显影露出的部位。在这里层厚能够直到500微米(步骤305)。
iv)去掉胶层和区别腐蚀铜和钛以及与载体分离(步骤306)。
也可以这样进行,在背离衬底1表面的电绝缘材料的覆层3的上表面上涂覆一个掩膜,它使接触面以及用于在接触面210、载体1的外露部位和电绝缘材料的覆层3上延伸的导体带4,6的部位空着,然后将导电材料的覆层4整个平面地涂覆到掩膜和接触面210和112以及被掩膜空着的部位上。然后去除具有位于掩膜上的覆层4的掩膜,因此只在无掩膜的部位上保留其余的平面接触的接触面210和在接触面210、载体1的外露部位和电绝缘材料的覆层3上延伸的导体带4,6。
在各种情况下都接着制备一个由具有一个表面的器件2构成的装置,在该表面上设置一个电接触面210,在该装置中在表面上涂覆一个电绝缘材料的覆层3形式的绝缘体,它紧密地顶靠在表面上并粘附在表面上并且在该装置中使电绝缘材料的覆层3对于接触面分别具有窗口31,在窗口中这个接触面从电绝缘材料的覆层3中露出来并平面地与一个覆层4并例如也与导电材料的覆层6接触。这个装置的特殊结构由上面的描述中给出。
在图2中示出的装置通过一个与图1所示的类似的加工方法生产。在此器件2的单端固定的接触结构3,4,6通过下列的工艺步骤进行加工:
-将也可以以一个模块形式呈现的器件2放置在一个或多个适当成形的、通过特富龙或类似塑料覆层的载体1上。
-在真空中在压力和温度条件下在器件2和载体1上层合一个塑料薄膜形式的电绝缘材料的覆层3。
-通过激光烧蚀去掉可能在器件2的接线片形式的接触面上的塑料薄膜形式的电绝缘材料的覆层3。
-尤其通过溅射和蒸镀涂覆一个薄的、可靠粘附的金属层、例如钛粘附层形式的导电材料的覆层4。
-涂覆和形成一个胶层结构,例如通过旋涂、喷胶、电泳涂胶并接着进行光刻或通过印刷工艺。
-通过具有一个可选择的接着进行的镍金覆盖层的较厚铜导电层6电镀地加厚导电材料的覆层4的外露的金属结构。
-可能地通过接着的局部激光烧蚀或通过在顶模工艺中的塑料覆盖层7或作为顶盖由一个第二薄膜实现器件2的遮盖。
-使器件2和所加工的金属/塑料接触结构3,4,6与载体1脱离。
-为了实现良好的钎焊性,可能局部地腐蚀金属结构6的粘附层4。
-可能使所产生的单端固定的金属/塑料接触结构3,4,6成形。
在此所述接触结构(接线接触结构)直接在器件2上产生。由此省去了在器件与由现有技术已知的一个导线框架或三脚架形式的接触部件之间的连接工艺,即钎焊或导线粘接。在此所产生的用于直接电连接的铜膜形式的导体带4,6是低感应的,适用于大电流并且是经济的。此外所述工艺与一个粘连接相比具有一个非常矮的结构高度,因为省去粘接环。所述工艺也适用于加工模块形式的器件的接线结构,这些模块含有多个单个的器件。
如同由图2可以看到的那样,在加工单端固定的接触结构3,4,6期间,所述器件2在一个铜覆层上设置在用于排出热量(降温)的机构8上。所述器件2和用于排出热量的机构8在此被载体1包围,它们设置在器件2和用于排出热量的机构8的左侧和右侧。代替两个载体1也可以使用同一个载体的两个分载体。尤其是当要实现的接触结构能够使器件2圆周地、即从所有四个侧面可以接触的时候,所述分载体可以属于同一载体,它以一个载体板的形式围绕器件延伸,该器件设置在这个载体板的一个缺口里面。
在步骤306中具有单端固定的接触结构3,4,6和塑料覆盖层7的器件2与载体1分离并在步骤307中装到其确定位置上。
为此如同在图3的截面图和图4的俯视图中所示的那样,使器件2在其用于排出热量的机构8上通过一个导热的粘接剂8或者一个这样的薄膜与一个金属外壳9粘接。在接触面上,在该接触面上铜覆层与一个粘附层形式的导电材料的覆层4脱离,较厚的导电铜覆层6与一个电路板、尤其是一个PCB电路板的导体带11连接,这一点通过钎焊连接12实现。在所示实施例中所述器件2是一个功率晶体管并且相应地在电路板10上存在用于晶体管的集电极C、控制极GATE和发射极E的导体带11,这个晶体管与它们连接。
按照图5的实施例与按照图2的实施例的不同之处在于,所述器件2不是设置在载体1周围而是设置在载体1上面。此外该载体1在两个方面特殊地构成。一方面它具有一个支座13,器件2在加工过程期间可靠地固定在该支座里面。另一方面在载体中设置推出器14,它们可以从载体1中移出来并在移出来时使器件2与单端固定的接触结构3,4,6、即可能还局部存在的电绝缘材料的覆层3和由导电材料的覆层4和较厚导电层6构成的导体带4,6并与一个顶盖形式的覆盖层7一起被推出。
所述步骤306除了推出形式的分离以外也包括腐蚀,尤其是路径腐蚀,它在一个通过钛粘附层构成的导电材料的覆层4的位置上,在该位置上以后要钎焊较厚的导电铜覆层6。
在图6中示出这个器件2与单端固定的接触结构和覆盖层的单独、可搬运的状态。单端固定的接触结构3,4,6的导体带4,6通过其加工过程具有一个铜膜的形式并且因此特别适用于低感应和大电流。
在图7和8中示出的实施例与在图5和6中示出的实施例的不同之处在于,所述器件2以一个芯片的形式不是设置在载体的一个支座里面而是设置在载体1的一个凹下里面,其深度基本等于器件的高度并且其垂直于其深度的尺寸基本等于器件垂直于其高度的尺寸。由此使在器件2上加工出来的接触结构3,4,6不向着在加工器件2时位于下面的器件2侧面下降,而是基本保留在加工时位于上面的器件2的侧面的水平面上或者该水平面以上。其优点是,通过使器件2通过其在加工时位于上面的侧面指向一个衬底地设置在衬底上,使要被接触的较厚导电覆层6不必在其接触面上才与粘附层或薄膜分离,因为可以直接利用其在加工时向上指向的、裸露的用于钎焊的表面。为此,通过由SMD技术已知的方法使接触面610、即可钎焊的引线准确定位且钎焊在导体带4,6的较厚导电层6上,这一点也适用于其它实施例。但是在已配备器件的PCB电路板上也可以使用与在TAB中相同的熨焊技术。
Claims (21)
1.一种用于加工一个具有接触结构的器件(2)的方法,其中该器件(2)具有一个电接触面(210),其特征在于,
-使一个电绝缘材料的覆层(3)涂覆到器件(2)和一个设置在器件上和/或器件周围的载体(1)上,
-使所述器件的电接触面(210)在涂覆电绝缘材料的覆层(3)时至少部分地空着和/或在涂覆电绝缘材料的覆层(3)之后外露,
-使一个导电材料的覆层(4)涂覆到电绝缘材料的覆层(3)和器件的电接触面(210)上,
-其中使电绝缘材料的覆层(3)与载体(1)分离。
2.如权利要求1所述的方法,其特征在于,
-使导电材料的覆层(4)附加地涂覆到载体(1)的不被电绝缘材料的覆层(3)遮盖的部位上,
-其中使导电材料的覆层(4)与载体(1)分离。
3.尤其如权利要求1所述的、用于加工一个具有接触结构的器件(20)的方法,其中该器件(2)具有一个电接触面(210),其特征在于,
-使一个电绝缘材料的覆层(3)涂覆到器件(2)上,
-使所述器件的电接触面(210)在涂覆电绝缘材料的覆层(3)时至少部分地空着和/或在涂覆电绝缘材料的覆层(3)之后外露,
-使一个导电材料的覆层(4)涂覆到电绝缘材料的覆层(3)、器件的电接触面(210)和一个设置在器件和/或器件周围的载体(1)上,
-其中使导电材料的覆层(4)与载体(1)分离。
4.如上述权利要求中任一项所述的方法,其特征在于,所述器件、电绝缘材料的覆层(3)和/或导电材料的覆层(4)至少局部地被浇铸和/或遮盖。
5.如上述权利要求中任一项所述的方法,其特征在于,使用一个载体(1),它至少局部地具有一个微小的表面粘附,尤其是特富龙覆层的和/或由特富龙制成。
6.如上述权利要求中任一项所述的方法,其特征在于,使用一个载体(1),它具有一个用于器件的支座。
7.如上述权利要求中任一项所述的方法,其特征在于,使用一个载体(1),它具有一个用于分离的推出器。
8.如上述权利要求中任一项所述的方法,其特征在于,所述器件的电接触面(210)在涂覆电绝缘材料的覆层(3)时至少部分地空着和/或在涂覆电绝缘材料的覆层(3)之后外露,其方法是在电绝缘材料的覆层(3)中开着和/或打开一个在尺寸上大于器件侧面和/或表面60%、尤其是大于80%的窗口,该窗口在该器件表面上开着和/或打开。
9.如上述权利要求中任一项所述的方法,其特征在于,所述器件的电接触面(210)在涂覆电绝缘材料的覆层(3)时至少部分地空着和/或在涂覆电绝缘材料的覆层(3)之后外露,通过在电绝缘材料的覆层(3)中开着和/或打开一个在尺寸上不大于器件侧面和/或表面99.9%的窗口,尤其是不大于95%,该窗口在该器件表面上开着和/或打开。
10.如上述权利要求中任一项所述的方法,其特征在于,所述电绝缘材料的覆层(3)借助于一个或多个后面的工作步骤实现涂覆:帘铸,浸入、尤其是单面浸入,电晕、尤其是静电电晕、印刷、尤其是丝网印刷,顶模,扩散,旋涂,层合一个薄膜。
11.如上述权利要求中任一项所述的方法,其特征在于,对于电绝缘材料的覆层(3)使用一个由聚酰亚胺基、聚乙烯胺基、多酚基、聚醚酮基和/或环氧基的塑料制成的薄膜。
12.如上述权利要求中任一项所述的方法,其特征在于,所述电绝缘材料的覆层(3)通过一个层合薄膜涂覆并且在层合薄膜之后执行一个退火步骤。
13.如上述权利要求中任一项所述的方法,其特征在于,所述电绝缘材料的覆层(3)具有一个25至150微米的厚度。
14.如上述权利要求中任一项所述的方法,其特征在于,所述器件(2)是一个功率电子器件,尤其是一个功率半导体。
15.如上述权利要求中任一项所述的方法,其特征在于,所述器件(2)至少70微米厚,尤其是至少100微米厚。
16.如上述权利要求中任一项所述的方法,其特征在于,所述器件构成一个表面轮廓并且其中电绝缘材料的覆层(3)这样涂覆到器件(2)上,使得电绝缘材料的覆层(3)衔接所构成的表面轮廓。
17.如上述权利要求中任一项所述的方法,其特征在于,所述器件的电接触面(210)至少局部地通过激光烧蚀露出。
18.如上述权利要求中任一项所述的方法,其特征在于,对于电绝缘材料的覆层(3)使用一个光敏材料并且所述器件的电接触面(210)至少局部地通过一个光刻工艺露出。
19.如上述权利要求中任一项所述的方法,其特征在于,所述导电材料的覆层(4)以多个上下设置的不同的导电材料分覆层涂覆,其中尤其一个上分覆层通过电镀生长涂覆。
20.如上述权利要求中任一项所述的方法,其特征在于,为了加工一个多层装置多次地执行步骤涂覆电绝缘材料的覆层、露出接触面和涂覆导电材料的覆层。
21.一种通过如权利要求1至20中任一项所述的方法制造的装置。
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EP (1) | EP1597755A2 (zh) |
JP (1) | JP2006519475A (zh) |
KR (1) | KR20050106467A (zh) |
CN (1) | CN1754255A (zh) |
DE (1) | DE10308928B4 (zh) |
WO (1) | WO2004077546A2 (zh) |
Families Citing this family (15)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP1597757A2 (de) * | 2003-02-28 | 2005-11-23 | Siemens Aktiengesellschaft | Verbindungstechnik für leistungshalbleiter mit einer der oberflächenkontur folgenden schicht aus elektrisch isolierendem material |
DE102004057494A1 (de) * | 2004-11-29 | 2006-06-08 | Siemens Ag | Metallisierte Folie zur flächigen Kontaktierung |
DE102006012007B4 (de) * | 2005-03-16 | 2013-05-16 | Infineon Technologies Ag | Leistungshalbleitermodul mit oberflächenmontierbaren flachen Außenkontakten und Verfahren zur Herstellung desselben und dessen Verwendung |
DE102005037321B4 (de) | 2005-08-04 | 2013-08-01 | Infineon Technologies Ag | Verfahren zur Herstellung von Halbleiterbauteilen mit Leiterbahnen zwischen Halbleiterchips und einem Schaltungsträger |
DE102006013076A1 (de) * | 2006-03-22 | 2007-09-27 | Semikron Elektronik Gmbh & Co. Kg | Leistungshalbleiterbauelement mit Passivierungsschicht und zugehöriges Herstellungsverfahren |
US7524775B2 (en) | 2006-07-13 | 2009-04-28 | Infineon Technologies Ag | Method for producing a dielectric layer for an electronic component |
DE102007007142B4 (de) * | 2007-02-09 | 2008-11-13 | Infineon Technologies Ag | Nutzen, Halbleiterbauteil sowie Verfahren zu deren Herstellung |
DE102007017831B8 (de) * | 2007-04-16 | 2016-02-18 | Infineon Technologies Ag | Halbleitermodul und ein Verfahren zur Herstellung eines Halbleitermoduls |
US7759777B2 (en) | 2007-04-16 | 2010-07-20 | Infineon Technologies Ag | Semiconductor module |
US7879652B2 (en) * | 2007-07-26 | 2011-02-01 | Infineon Technologies Ag | Semiconductor module |
US7955901B2 (en) | 2007-10-04 | 2011-06-07 | Infineon Technologies Ag | Method for producing a power semiconductor module comprising surface-mountable flat external contacts |
US8618674B2 (en) * | 2008-09-25 | 2013-12-31 | Infineon Technologies Ag | Semiconductor device including a sintered insulation material |
US8710665B2 (en) | 2008-10-06 | 2014-04-29 | Infineon Technologies Ag | Electronic component, a semiconductor wafer and a method for producing an electronic component |
DE102009036418B4 (de) * | 2009-08-06 | 2011-06-22 | Siemens Aktiengesellschaft, 80333 | Wellenleiter, insbesondere beim Dielektrikum-Wand-Beschleuniger |
DE102012216926A1 (de) * | 2012-09-20 | 2014-03-20 | Jumatech Gmbh | Verfahren zur Herstellung eines Leiterplattenelements sowie Leiterplattenelement |
Family Cites Families (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE9109295U1 (de) * | 1991-04-11 | 1991-10-10 | Export-Contor Außenhandelsgesellschaft mbH, 8500 Nürnberg | Elektronische Schaltungsanordnung |
US5291066A (en) * | 1991-11-14 | 1994-03-01 | General Electric Company | Moisture-proof electrical circuit high density interconnect module and method for making same |
US5353498A (en) * | 1993-02-08 | 1994-10-11 | General Electric Company | Method for fabricating an integrated circuit module |
CA2173123A1 (en) * | 1993-09-30 | 1995-04-06 | Paul M. Zavracky | Three-dimensional processor using transferred thin film circuits |
US5637922A (en) * | 1994-02-07 | 1997-06-10 | General Electric Company | Wireless radio frequency power semiconductor devices using high density interconnect |
US5653019A (en) * | 1995-08-31 | 1997-08-05 | Regents Of The University Of California | Repairable chip bonding/interconnect process |
US6127199A (en) * | 1996-11-12 | 2000-10-03 | Seiko Epson Corporation | Manufacturing method of active matrix substrate, active matrix substrate and liquid crystal display device |
US6706546B2 (en) * | 1998-10-09 | 2004-03-16 | Fujitsu Limited | Optical reflective structures and method for making |
SG83785A1 (en) * | 1999-04-30 | 2001-10-16 | Esec Trading Sa | Apparatus and method for mounting semiconductor chips on a substrate |
DE10004410A1 (de) * | 2000-02-02 | 2001-08-16 | Infineon Technologies Ag | Halbleiterbauelement mit an der Unterseite befindlichen Kontakten und Verfahren zur Herstellung |
CN100468670C (zh) * | 2003-02-28 | 2009-03-11 | 西门子公司 | 带有大面积接线的功率半导体器件的连接技术 |
EP1597757A2 (de) * | 2003-02-28 | 2005-11-23 | Siemens Aktiengesellschaft | Verbindungstechnik für leistungshalbleiter mit einer der oberflächenkontur folgenden schicht aus elektrisch isolierendem material |
-
2003
- 2003-02-28 DE DE10308928A patent/DE10308928B4/de not_active Expired - Fee Related
-
2004
- 2004-01-15 JP JP2005518520A patent/JP2006519475A/ja not_active Withdrawn
- 2004-01-15 EP EP04702322A patent/EP1597755A2/de not_active Withdrawn
- 2004-01-15 US US10/547,174 patent/US7368324B2/en not_active Expired - Fee Related
- 2004-01-15 KR KR1020057016079A patent/KR20050106467A/ko not_active Application Discontinuation
- 2004-01-15 WO PCT/EP2004/000263 patent/WO2004077546A2/de active Search and Examination
- 2004-01-15 CN CNA2004800052104A patent/CN1754255A/zh active Pending
Also Published As
Publication number | Publication date |
---|---|
WO2004077546A3 (de) | 2005-05-19 |
US20060248716A1 (en) | 2006-11-09 |
KR20050106467A (ko) | 2005-11-09 |
WO2004077546A2 (de) | 2004-09-10 |
DE10308928A1 (de) | 2004-09-09 |
EP1597755A2 (de) | 2005-11-23 |
JP2006519475A (ja) | 2006-08-24 |
US7368324B2 (en) | 2008-05-06 |
DE10308928B4 (de) | 2009-06-18 |
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