CN1708857A - 半导体组件及其制造方法 - Google Patents

半导体组件及其制造方法 Download PDF

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CN1708857A
CN1708857A CNA2003801021607A CN200380102160A CN1708857A CN 1708857 A CN1708857 A CN 1708857A CN A2003801021607 A CNA2003801021607 A CN A2003801021607A CN 200380102160 A CN200380102160 A CN 200380102160A CN 1708857 A CN1708857 A CN 1708857A
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D·瑞斯特
C·魏因特劳布
J·F·布勒
J·奇克
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Abstract

一种具有源极侧晕圈区(120)的绝缘栅极场效应半导体组件(100)，以及制造该半导体组件(100)的方法。在半导体衬底(102)上形成栅极结构(112)。在半导体衬底(102)中形成源极侧晕圈区(120)。在形成源极侧晕圈区(120)之后，在邻接栅极结构(112)的相反两边形成间隔体(127，128，152，154)。利用斜角注入在半导体衬底(102)中形成源极延伸区(136A)和漏极延伸区(138A)。该源极延伸区(136A)延伸于栅极结构(112)之下，而漏极延伸区(138A)可以延伸于栅极结构(112)之下或侧向地从栅极结构(112)相隔开。在半导体衬底(102)中形成源极区(156)和漏极区(158)。

Description

半导体组件及其制造方法
技术领域
本发明通常涉及半导体组件，特别地涉及一种栅极边缘重叠延伸的半导体组件。
背景技术
例如微处理器、数字信号处理器、微控制器、存储装置，及其类似的集成电路一般均含有数百万个的绝缘栅极场效应晶体管(IGFET)。由于希望降低制造成本并增加电路速度，所以集成电路制造商缩小构成集成电路的绝缘栅极场效应晶体管的尺寸而使其可从单一片半导体晶片制造出更多的集成电路。虽然较小的晶体管可增加操作速度，但是例如减少源极-漏极击穿电压、增加结电容、以及不稳定的阈值电压的次生性能因素均对晶体管的性能造成负面的影响。整体而言，这些不良的性能影响称之为短沟道效应(short channel effects)。
一般技术为通过调节沟道区内的电场来缓和此短沟道效应，以使漏极耗尽区的尖峰横向电场(peak lateral electric field)最小化。用于降低横向电场的一种技术是使其包含源极和漏极延伸区。源极延伸区延伸入邻接栅极结构一侧边的硅衬底中，并且漏极延伸区延伸入邻接栅极结构另一侧边的硅衬底中。该源极和漏极延伸区延伸在栅极结构之下。该漏极延伸区可减少绝缘栅极场效应晶体管的漏极区的最大电场，因而可减少能够从漏极区穿隧进入栅极氧化物的电子数目。即使经此改善，漏极区内的电子数目仍足以产生栅极至漏极的隧道电流，而降低晶体管的性能。
因此，需要一种具有较低栅极至漏极隧道电流的半导体组件以及制造该半导体组件的方法。
发明内容
本发明提供一种在源极和漏极延伸区以及源极和漏极区形成之前形成有源极侧晕圈区(side halo region)的半导体组件以及制造该半导体组件的方法，以满足前述的需要。根据本发明的一个方面，本发明包括形成在第一导电类型的半导体材料上的栅极结构。在形成栅极结构之后，利用离子注入技术在邻接栅极结构的源极侧的半导体材料中形成源极侧晕圈区(halo region)。在形成源极侧晕圈区之后，在栅极结构的相反边上形成第一组的间隔体(spacer)，随后通过利用斜角注入来注入第二导电类型的掺杂物，以形成源极和漏极延伸区。邻接第一组间隔体形成第二组间隔体，并且在半导体材料中形成源极和漏极区。
根据另一方面，本发明包括具有其上设置了栅极结构的半导体材料。源极侧晕圈区邻接栅极结构的源极侧。源极延伸区邻接于栅极结构的第一侧边并延伸在栅极结构之下，且漏极延伸区邻接于栅极结构的第二侧边并延伸在栅极结构的第二侧边之下。源极区邻接于栅极结构的第一侧边并由该栅极结构的第一侧边所隔开，且漏极区邻接于栅极结构的第二侧边并由该栅极结构的第二侧边所隔开。
附图说明
通过结合附图阅读下列说明可更好的理解本发明，相同的组件用相同的组件符号表示，其中：
图1至6为根据本发明实施例的部分绝缘栅极场效应晶体管的高度放大的剖面图。
具体实施方式
一般而言，本发明提供一种用于制造例如绝缘栅极半导体器件的半导体组件的方法。绝缘栅极半导体器件也称为绝缘栅极场效应晶体管、场效应晶体管、半导体组件、或半导体器件。根据本发明的一个实施例，利用斜角注入(angled implant)形成非对称源极/漏极延伸区。利用非对称注入可使源极延伸区和栅极结构之间重叠，因而降低晶体管的源极侧电阻。此外，非对称注入可减少栅极结构和漏极延伸区之间的重叠，因而可降低栅极至漏极(gate-to-drain)的隧道电流及漏极侧的米勒电容(Miller capacitance)。再者，此斜角注入不需昂贵的掩膜处理过程即可形成非对称源极和漏极延伸区。根据本发明的另一实施例，源极侧晕圈区形成在其它掺杂区形成之前，而使该晕圈区更接近沟道区的中央，因此当半导体组件内包含非对称源极和漏极延伸区时可提供较佳的阈值电压下拉(roll-off)控制。
图为1是根据本发明的实施例在开始处理阶段所局部完成的绝缘栅极场效应晶体管100的部分放大剖面图。图1中显示了具p型导电性的半导体衬底或材料102，该半导体衬底或材料102含有主要表面104。根据实例，半导体衬底102为具有<100>晶格方向的硅，并且具有每立方厘米含1×1016个离子(ions/cm3)量级的p型掺杂物浓度。或者，半导体衬底102可由具有<100>晶格方向的高掺杂的硅晶片以及设置在该半导体衬底102上的低掺杂的外延层(epitaxial layer)所构成。其它适合衬底102的材料包括硅锗、锗、绝缘体上硅(Silicon-On-Insulator，SOI)等。本发明并非仅局限于上述衬底102的导电类型。根据本发明的实施例，选择用于形成N沟道绝缘栅极场效应晶体管的导电类型。然而，该半导体衬底也可选择用于形成P沟道绝缘栅极场效应晶体管或例如互补金属氧化物半导体(CMOS)晶体管的互补绝缘栅极场效应晶体管的导电类型。此外，可在衬底102中形成例如P型导电性衬底中的N阱(N-well)或N型导电性衬底中的P阱(P-well)的掺杂阱。P-沟道和N-沟道晶体管形成在各自的掺杂阱内。应了解图式中虽未显示，但可在半导体衬底102或掺杂阱内进行阈值电压调节注入。
在主要表面104上形成介电材料层106。介电层106作为栅极介电材料并且可由本领域技术人员所熟知的技术而形成，包括热氧化作用、化学气相沉积、以及其它类似方法。介电层106的厚度约从5埃()至约500埃。利用例如化学气相沉积技术在介电层106上形成多晶硅层108。适当的多晶硅层108厚度范围为介于约500埃和约2,000埃之间。作为实例，介电层106的厚度为200埃以及多晶硅层108的厚度为1,500埃。在多晶硅层108上沉积光刻胶层，并图形化该光刻胶层以形成蚀刻掩膜110。光刻胶层的沉积和图形化技术已为本领域技术人员所熟知。
现在参考图2，利用蚀刻多晶硅常用的蚀刻化学技术蚀刻多晶硅层108。作为实例，利用各向异性反应性离子蚀刻(RIE)蚀刻多晶硅层108。蚀刻多晶硅的方法已为本领域技术人员所熟知。在除去多晶硅层108的暴露部分之后，蚀刻化学技术被用于各向异性蚀刻氧化物层106。此各向异性蚀刻氧化物层106终止于主要表面104上。然后移除蚀刻掩膜层110。多晶硅层108和介电层106的残留部分108A和106A分别形成具有侧壁114和116及上表面118的栅极结构112。部分118A用作栅极导体，部分106A用作栅极氧化物或栅极电介质。
继续参考图2，在半导体衬底102内注入P型导电性的掺杂物，例如硼或铟，以形成掺杂区120。掺杂区120被称为源极侧晕圈区。注入最好是呈角度或斜角进行注入，其相对于大致上垂直于(或法线)主要表面104的方向呈角度θ，其中角度θ为小于90度并且较佳的是从约20度至约50度间的范围。角度θ的角度更佳的是介于从约35度至约45度之间的范围。源极侧晕圈注入(halo implant)的一组适当参数包括注入离子量介于约1×1013离子/平方厘米和约1×1016离子/平方厘米之间的P型导电性掺杂物，以及利用范围介于约100电子伏特(eV)和约50千电子伏特(KeV)之间的注入能量。角度掺杂物注入由箭头124代表。此处用于形成N-沟道绝缘栅极场效应晶体管的注入能量和注入剂量仅供举例的用途，而本发明并非仅局限于该范围的值。如本领域技术人员所熟知，P-沟道绝缘栅极场效应晶体管可有不同的注入能量和注入剂量。例如，用于在P-沟道绝缘栅极场效应晶体管中形成晕圈区的适当注入剂量可介于约1KeV至约100KeV之间的范围。注入物可利用快速热退火(RTA)工艺或传统的炉管退火工艺进行处理。作为实例，通过加热至约800度摄氏(℃)和约1,100℃的范围间的温度将半导体器件100退火。半导体组件100的退火可使掺杂物在垂直和横向方向扩散。
仍参考图2，介电材料层126沉积在栅极结构112以及主要表面104的暴露部分之上。作为实例，介电材料层126通过例如化学气相沉积的沉积技术或通过诸如栅极导体108A和硅102的氧化的生长技术被氧化形成。较佳的氧化物层126的厚度为介于约50埃和约1,500埃之间的范围。
现在参考图3，氧化物层126被各向异性地蚀刻而形成间隔体127和128，并暴露出主要表面104。例如砷的N型导电性掺杂物被注入半导体材料102而形成掺杂区136和138。掺杂区136和138的部分136A和138A分别作为源极和漏极的延伸。此延伸注入最好是一种单扭(single twist)、成角度或斜角的注入，可以使注入相对于大致上垂直于(或法线)主要表面104的方向(以虚线122表示)成角度α，其中角度α为小于90度并且较佳的是从约0度至约25度的范围。角度α的范围更佳的是介于从约0度至约10度之间的范围。如本领域技术人员所熟知，单扭注入时晶片不随着垂直主要表面104的轴旋转，以便能够进行后续的非对称性延伸注入。源极和漏极延伸注入的适当参数包括使用范围在约100eV和约20keV间的注入能量来注入剂量范围介于约1×1014离子/平方厘米和约1×1016离子/平方厘米之间的N型导电性掺杂物。角度的掺杂物注入由箭头130代表。该能量和剂量仅供举例的用途，本发明并非以此为限。注入物可利用快速热退火(RTA)工艺或传统的炉管退火工艺进行处理。作为实例，通过加热至约800℃和约1,100℃的范围间的温度对半导体器件100进行退火。半导体组件100的退火可使掺杂物在垂直和横向方向扩散。因此，N型掺杂物在栅极结构112之下从侧边114向栅极结构112的侧边116扩散，并且可在该栅极结构112的侧边116的下扩散。
由于源极和漏极延伸区136A和138A分别利用单扭、成倾斜角度注入而形成，所以对栅极结构112而言是非对称的。源极延伸区136A延伸入半导体衬底102并且从侧边114延伸于栅极结构112之下，同时漏极延伸区138A延伸入半导体衬底102并且可从另一侧边116延伸于栅极结构112之下或从栅极结构112的侧边116横向地隔开。因此，本发明着重构思在栅极结构112之下延伸的漏极延伸区138A的实施例，以及未在栅极结构112之下延伸的漏极延伸区138A的实施例。对于从侧边116隔开漏极延伸区138A的实施例而言，介于漏极延伸区138A和侧边116之间的距离D在某种程度上视注入角度和栅极结构112的高度而定。此外，退火工艺影响漏极延伸区138A和侧边116之间的距离。当退火温度越高且退火时间越长时，漏极延伸区138A朝侧边116扩散的距离越近。由于源极延伸区136A靠近第一侧边114，故其可谓接近或邻接第一侧边114。同理，漏极延伸区138A可谓接近或邻接第二侧边116。
又参考图3，在栅极结构112、间隔体127和128、以及主要表面104的暴露部分上形成具有厚度介于约200埃和约1,500埃之间的硅氮化物层146。作为实例，利用化学气相沉积技术沉积硅氮化物层146。或者，该硅氮化物层146可为氧化物层或任何适合形成间隔体的材料层。
现在参考图4，各向异性地蚀刻硅氮化物层146以形成间隔体152和154。因此，间隔体127介于间隔体152和栅极结构112的侧边114之间，且间隔体128介于间隔体154和栅极结构112的侧边116之间。执行零角度的源极/漏极注入以形成源极区156和漏极区158。因此，源极区156由间隔体152和侧边114隔开并对准间隔体152和侧边114，而漏极区158由间隔体154和侧边116隔开并对准间隔体154和侧边116。该源极/漏极注入也掺杂栅极结构112。源极和漏极注入的一组适当参数包括注入例如介于约1×1014离子/平方厘米和约1×1016离子/平方厘米之间剂量范围的磷的N型导电性掺杂物，以及利用介于约5KeV和约100KeV之间的注入能量。以约介于800℃和约1,100℃之间的温度进行半导体组件100的退火。
又参考图4，进行湿式蚀刻以移除任何沿着栅极导体108A上表面118的氧化物以及任何设置在主要表面104上的氧化物层。难熔金属层160沉积于上表面118、间隔体152和154、以及主要表面104的暴露部分。作为实例，难熔金属层160为具有厚度范围介于约50埃和约300埃之间的钴。
现在参考图5，加热难熔金属层160至600℃和700℃之间的温度。此热处理使钴和硅发生反应，而在钴和硅接触的所有区域中形成硅化钴(CoSi2)。因此，硅化钴164形成在栅极导体108A，硅化钴166形成在源极区164，以及硅化钴168形成在漏极区158。置于间隔体152和154上的钴的部分则仍保持未反应的状态。应了解本发明并非仅局限于使用硅化物。例如，也可使用其它适合的硅化物包括硅化钛(TiSi)、硅化铂(PtSi)、硅化镍(NiSi)、以及类似的硅化物。如同本领域技术人员所了解，在形成硅化物的过程中消耗了硅，并且所消耗的硅量为所形成的硅化物类型的函数。因此，显示了硅化物164延伸入栅极导体108A，硅化物166延伸入源极区156、以及硅化物168延伸入漏极区158。
仍参考图5，利用本领域技术人员所熟知的工艺移除未反应的钴。移除未反应的钴可使栅极导体108A、源极区156、以及漏极区158相互电性隔离。
现在参考图6，在包括硅化物区域的结构上形成介电材料层170。作为实例，介电材料层170为具有厚度范围介于约5,000埃和15,000埃之间的氧化物。在氧化物层170中形成开口而暴露出硅化物层164、166和168的部分。利用本领域技术人员所熟知的技术，形成接触暴露的硅化物层164、166和168的电导体或电极。更明确而言，是指接触栅极硅化物层164的栅极电极174，接触源极硅化物层166的源极电极176，以及接触漏极硅化物层168的漏极电极178。
现在应了解本发明已经提供了绝缘栅极半导体组件以及制造该半导体组件的方法。根据本发明的一个方面，该组件具有非对称源极和漏极延伸区，该源极延伸区延伸于栅极结构之下以及漏极延伸区延伸于栅极结构之下，并且分别对准至栅极结构的一个边缘或由该栅极结构横向隔开。在栅极结构之下形成源极延伸区(即，增加栅极结构和源极侧延伸区的重叠面积)可降低半导体组件的源极侧的电阻并增加栅极至源极的电压，因而可提供更多的驱动电流。此可改善半导体组件的直流特性。此外，减少或消除栅极结构和漏极侧延伸区的重叠面积可降低漏极侧的米勒电容，此可改善半导体组件的交流特性。再者，减少栅极结构和漏极侧延伸区的重叠面积可降低栅极至漏极的直接隧道电流。此源极侧非对称晕圈区可减少靠近漏极延伸区的沟道掺杂，以改善半导体组件的直流特性。减少靠近漏极延伸区的沟道掺杂也可降低结电容，因而改善半导体组件的交流特性。当半导体组件为绝缘体上硅(SOI)器件时，此改善可获得莫大的益处。在形成其它掺杂区之前形成晕圈区，可在利用非对称延伸区时提供较佳的阈值电压下拉控制，并且使晕圈区的形成较接近沟道区的中央，因而可避免在形成延伸区时的反掺杂。
虽然此处已揭示了一些较佳的实施例以及方法，但本领域技术人员从上述的揭示中应了解，在不背离本发明的精神和范围内这些实施例及方法可加以变化和修改。

Claims (10)

1.一种制造半导体组件(100)的方法，包括：
提供具有主要表面(104)的第一导电类型的半导体材料(102)；
在该主要表面(104)上形成栅极结构(112)，该栅极结构(112)具有第一(114)和第二(116)侧边及上表面(118)；
利用斜角注入在该半导体材料(102)中非对称地注入第一导电类型的掺杂物，而该斜角注入以相对于垂直该主要表面(104)的方向小于90度的角度进行注入，其中一部分掺杂物为邻接该栅极结构(112)的第一侧边(114)并且作为第一晕圈区(120)；以及
在该半导体材料(102)中形成第二导电类型的第一(156)和第二(158)掺杂区，该第一掺杂区(156)接近该栅极结构(112)的第一侧边(114)以及该第二掺杂区(158)接近该栅极结构(112)的第二侧边(116)。
2.如权利要求1所述的方法，其中将该掺杂物非对称地注入到该半导体材料(102)中包括以介于20度和50度范围之间的角度进行注入。
3.如权利要求1所述的方法，其中将该掺杂物非对称地注入到该半导体材料(102)中包括以介于35度和45度范围之间的角度进行注入。
4.如权利要求1所述的方法，还包括：
邻接该栅极结构(112)的第一侧边(114)形成第一间隔体(127)以及邻接该栅极结构(112)的第二侧边(116)形成第二间隔体(128)；以及
利用斜角注入在该半导体材料(102)中注入该第二导电类型的掺杂物，而该斜角注入以相对于垂直该主要表面(104)方向小于90度的角度进行注入，其中一部分掺杂物邻接该栅极结构(112)的第一侧边(114)并且作为第一延伸区(136A)，其中该第一延伸区(136A)从该第一侧边(114)延伸至该栅极结构(112)之下。
5.如权利要求4所述的方法，其中一部分掺杂物邻接该栅极结构(112)的第二侧边(116)并且作为第二延伸区(138A)。
6.如权利要求5所述的方法，其中该第二延伸区(138A)从该栅极结构(112)的第二侧边(116)隔开。
7.一种制造半导体组件(100)的方法，包括：
提供具有主要表面(104)的第一导电类型的半导体材料(102)；
在该主要表面(104)上形成栅极结构(112)，该栅极结构(112)具有第一(114)和第二(116)侧边及上表面(118)；
邻接该栅极结构(112)的第一侧边(114)形成第一导电类型的晕圈区(120)；
邻接该栅极结构(112)的第一侧边(114)形成第一间隔体(127)以及邻接该栅极结构(112)的第二侧边(116)形成第二间隔体(128)；
利用斜角注入在该半导体材料(102)中注入第二导电类型的掺杂物，而该斜角注入以相对于垂直该主要表面(104)的方向为介于0度和90度之间的角度进行注入，并且其中一部分掺杂物邻接该栅极结构(112)的第一侧边(114)及延伸于该栅极结构(112)之下并且作为第一掺杂延伸区(136A)，而该第二导电类型的另一部分掺杂物邻接该栅极结构(112)的第二侧边(116)并且作为第二掺杂延伸区(138A)；
在邻接该第一(127)和第二(128)间隔体处分别形成第三(152)和第四(154)间隔体；
在该半导体材料(102)中形成第二导电类型的源极区(156)，该源极区(156)由该第一(127)和第三(152)间隔体从该第一侧边(114)隔开；以及
在该半导体材料中形成该第二导电类型的漏极区(158)，该漏极区(158)由该第二(128)和第四(154)间隔体从该第二侧边(116)隔开。
8.如权利要求7所述的方法，其中形成该晕圈区(120)包括利用斜角注入在该半导体材料(102)中注入该第一导电类型的掺杂物，其中该斜角注入以相对于垂直该主要表面(104)的方向为介于20度和50度之间的角度进行注入。
9.一种半导体组件(100)，包括：
具有主要表面(104)的半导体材料(102)；
设置在该主要表面(104)上的栅极结构(112)，该栅极结构(112)具有第一(114)和第二(116)侧边；
在该半导体材料(102)中的源极侧晕圈区(120)；
在该半导体材料(102)中的源极(136A)和漏极(138A)延伸区，其中该源极延伸区(136A)从该栅极结构(112)的第一侧边(114)在该栅极结构(112)之下延伸入该半导体材料(102)中，并且该漏极延伸区(138A)邻接该栅极结构(112)的第二侧边(116)；以及
在该半导体材料(102)中的源极(156)和漏极(158)区，该源极(156)和漏极(158)区邻接各自的源极(156A)和漏极(158A)延伸区。
10.如权利要求9所述的半导体组件(100)，还包括：
分别邻接该栅极结构(112)的第一(114)和第二(116)侧边的第一(127)和第二(128)间隔体，其中该漏极延伸区(138A)从该栅极结构(112)的第二侧边(116)横向地隔开；以及分别邻接该第一(127)和第二(128)间隔体的第三(152)和第四(154)间隔体，其中该源极(156)和漏极(158)区分别对准该第三(152)和第四(154)间隔体。
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