CN1705129A - 具有形成在电容器上的可流动绝缘层的半导体装置及其制造方法 - Google Patents

具有形成在电容器上的可流动绝缘层的半导体装置及其制造方法 Download PDF

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CN1705129A
CN1705129A CNA2004101034976A CN200410103497A CN1705129A CN 1705129 A CN1705129 A CN 1705129A CN A2004101034976 A CNA2004101034976 A CN A2004101034976A CN 200410103497 A CN200410103497 A CN 200410103497A CN 1705129 A CN1705129 A CN 1705129A
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insulation layer
capacitor
flowable insulation
insulating barrier
silicate glass
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CN100373624C (zh
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安尚太
辛东善
宋锡杓
辛钟汉
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SK Hynix Inc
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Abstract

本发明揭露一种具有形成在电容器上的可流动绝缘层的半导体装置,及其制造方法。尤其,该半导体装置包含:形成在衬底预定部分之上的电容器;通过在包括衬底和电容器的结果衬底结构上堆叠可流动绝缘层和未掺杂的硅酸盐玻璃层形成的绝缘层;和形成在绝缘层上的金属相互连接线。该方法包含下列步骤:在衬底的预定部分之上形成电容器;通过在包括衬底和电容器的结果衬底结构上,堆叠可流动绝缘层和未掺杂硅酸盐玻璃层,形成绝缘层;和在绝缘层上形成金属相互连接线。

Description

具有形成在电容器上的可流动绝缘层的半导体装置及其制造方法
技术领域
本发明是关于一种半导体装置,尤其是关于具有电容器上的绝缘层的半导体装置,及其制造方法。
背景技术
就如广为人知的,半导体存储器装置集成的微型化和大型化的趋势已被大大地要求,以确保包含在动态随机存取存储器(DRAM)单元中的电容器有足够的电容值。为了得到足够的电容值,介电材料是通过堆叠氧化铝(Al2O3)和氧化铪(HfO2)形成,或电容器的上电极和下电极是通过使用金属,如氮化钛(TiN)形成。
因此,在电容器上方形成绝缘层的案例中,绝缘层基本上应透过低温处理形成,以防止电容器的下层劣化,例如金属氧化,介电材料特性的劣化,和扩散。
此外,DRAM装置被分成其中形成电容器的单元区域和不形成电容器的外围电路区域。形成在单元区域的电容器应该具有较高的高度,以确保电容值。因此,在单元区域和外围电路区域之间的边界,会产生至少10,000的高度差。
因此,需要采用能够通过低温处理形成的绝缘材料和克服高度差,从而使能在电容器上的绝缘层的平坦化处理。
图1A到图1B为在制造DRAM装置的顺序处理中,用以在电容器上方形成绝缘层的传统方法的横截面图。尤其,图1A为传统形成的电容器,而图1B为传统形成在电容器上的绝缘层。
参照图1A,多个电容器C被形成在提供底绝缘层11、接触塞12和蚀刻停止层13的衬底结构上。每一个电容器C都包含要接触对应的接触塞12且具有圆柱形的下电极14,覆盖下电极14的介电层15,和形成在介电层15上的上电极16。电容器C典型是形成在DRAM单元区域,而非形成在外围电路区域。因此,在单元区域和外围电路区域之间的边界,存在有至少10,000的高度差。
参照图1B,使用等离子体增强化学气相沉积(PECVD)法形成的未掺杂的硅酸盐玻璃层(USG),被用作顶绝缘层D。对于使用PECVD法形成的基于USG的顶绝缘层D,会因先期沉积阶段的底部薄层17而产生接缝。该接缝会连续产生,通过中期沉积阶段的中间薄层18,到达最后沉积阶段的顶部薄层19。此接缝的产生是因为在单元区域和外围电路区域之间的边界的高度差。
接着,图1C为传统形成在电容器上的绝缘层的横截面图,其中绝缘层被平坦化,然后清洗。尤其在此图式中,说明有关用以在电容器上形成绝缘层中的传统方法的问题。
如图所示,通过PECVD法形成的基于未掺杂的硅酸盐玻璃层(USG)绝缘层D,透过化学机械抛光(CMP)处理或回蚀刻处理平坦化,然后清洗干净。此外,图中有一形成在产生接缝的区域的空腔20。
此空腔在后续的金属相互连接线形成处理期间会引发蚀刻残留物的产生,然后蚀刻残留物会变成在金属相互连接线之间形成桥的原因。
另一方面,为了要移除绝缘层D的空腔20,可以使用具有良好平坦化和台阶覆盖特性的高密度等离子体-化学气相沉积(HDP-CVD)法,形成绝缘层D。但是,HDP-CVD法的沉积机制是重复蚀刻和沉积的步骤,因此,会有在构成电容器的底层产生等离子体伤害的缺点。
再者,绝缘层D可以采用具有良好平坦化特性的臭氧-原硅酸四乙酯(ozone-tetraethylorthosilicate,O3-TEOS)。但是,若增加臭氧(O3)的浓度,以沉积厚度超过20,000的厚层,则O3-TEOS取决于显示上和下电极氧化的底层。
在使用能够回流(reflow)的硼磷硅酸盐玻璃(borophosphosilicate glass,BPSG)的情形下,因为当作绝缘层D的BPSG掺有硼(B)和磷(P),所以基本上要采用高温热处理,以在800℃的温度下回流BPSG。因此,不适合使用BPSG来执行低温处理。
发明内容
因此,本发明的目的是要提供一种具有通过执行低温处理,形成在电容器上,有良好平坦化特性,但不会使包含电容器的底层特性劣化的可流动绝缘层的半导体装置,及其制造方法。
根据本发明的一个方面,本发明提供一种半导体装置,包含:形成在衬底预定部分之上的电容器;通过堆叠可流动绝缘层和未掺杂的硅酸盐玻璃层,形成在含有衬底和电容器的结果衬底结构上的绝缘层;和形成在绝缘层上的金属相互连接线。
根据本发明的另一方面,本发明提供一种半导体装置的制造方法,包含下列步骤:在衬底的预定部分之上形成电容器;通过在含有衬底和电容器的结果衬底结构上,堆叠可流动绝缘层和未掺杂的硅酸盐玻璃层,形成绝缘层;和在绝缘层上形成金属相互连接线。
附图说明
根据下面参照相关附图的较佳实施例的说明,本发明上述的和其他的目的与特征将会变得更清楚,其中:
图1A和图1B为用以在动态随机存取存储器(DRAM)装置的电容器上,形成绝缘层的传统方法的横截面图;
图1C为当执行用以在电容器上形成绝缘层的传统方法时,所发生的问题的横截面图;
图2为根据本发明第一实施例,在电容器上形成绝缘层的横截面图;
图3为根据本发明第二实施例,在电容器上形成绝缘层的横截面图;及
图4为根据本发明第三实施例,在电容器上形成绝缘层的横截面图。
具体实施方式
下面,将根据本发明的较佳实施例,参照附图详细说明具有在电容器上的可流动绝缘层的半导体装置,及其制造方法。
图2到图4为各种衬底结构的横截面图,其中绝缘层是根据本发明的第一到第三实施例形成在电容器上。
首先,图2为根据本发明第一实施例的衬底结构范例。
如图所示,许多电容器C形成在提供第一绝缘层201,接触塞202和蚀刻停止层203的衬底上。每一个电容器C都包含与接触塞202接触且具有圆柱形形状的下电极204,覆盖下电极204的介电层205,和形成在介电层205上的上电极206。电容器C是形成在典型的DRAM单元区域中,而非形成在外围区域中。因此,在单元区域和外围区域之间的边界,存在至少约10,000的高度差。
接着,在电容器C上形成可流动绝缘层210,其在沉积可流动绝缘层210时,通过具有可流动性,不会在高度差很大的区域域产生接缝。
尤其,可流动绝缘层210可以通过采用旋涂介电(SOD)法形成,其中可以旋转速度约为60rpm到10000rprn的衬底上涂布液体源,如氢倍半硅氧烷(hydrogen silsesquioxane,HSQ)或甲基倍半硅氧烷(methylsilsesquioxane,MSQ)。此外,可流动绝缘层210也可以使用采用反应源,如四氢化硅(SiH4)和过氧化氢(H2O2)的低压化学气相沉积(LPCVD)法形成。尤其是使用反应源,如SiH4和H2O2的LPCVD法,是在小于约100Torr的压力下,在约-10℃到约40℃的温度,即放置晶圆的平板的温度的范围下,形成可流动绝缘层210。LPCVD是一种方法,其是因为在沉积处理时,在薄层中所含的反应剂具有很高的可流动性,所以沉积的薄膜相当地平坦。
在上述的沉积处理之后,接着执行热处理,以完全形成可流动绝缘层210。在此,热处理是为了移除存在在已沉积的可流动绝缘层210内部的杂质或水份,及密化可流动绝缘层210。热处理是通过炉管热处理和快速热处理其中之一,在氧气(O2)、臭氧(O3)、氮气(N2)、一氧化二氮(N2O)、或氢气(H2)和氧气(O2)的混合气体的气氛中进行。炉管热处理要在约200℃到约650℃的温度范围下执行超过约5分钟。快速热处理要在高于约300℃的温度下执行超过约1秒。
如上所示,此种型式的可流动绝缘层210,可以施以低温处理,且具有良好的平坦化特性。因此,可流动绝缘层210可以非常有用的方式,用以当作高度集成的和微型化半导体装置的层间绝缘层,即当作电容器上的绝缘层。
基于未掺杂的硅酸盐玻璃(USG)的绝缘层220,通过执行等离子体增强化学气相沉积(PECVD)法,形成在可流动绝缘层210之上。因为可流动绝缘层210已经减少衬底的高度差,所以不会在使用PECVD法形成的基于USG的绝缘层220中产生接缝。使用PECVD法形成的基于USG的绝缘层220,具有快速沉积速度和层稳定性的良好特性。
若单元区域和外围区域之间的高度差大于约10,000,则可以形成厚度范围从约500到约1,000的可流动绝缘层210,和厚度为约200到约30,000的基于USG的绝缘层220。下面,将形成在电容器C上的可流动绝缘层210和基于USG的绝缘层220称为第二绝缘层,在图2中以″D″表示。
接着,通过蚀刻或抛光已沉积的第二绝缘层D,上述的结果衬底结构被平坦化。在上述的平坦化处理之后,第二绝缘层D最好具有范围从约500到约5,000的剩余厚度。因为有可流动绝缘层210,所以不会产生接缝,因此在结果衬底结构被平坦化之后,不会在第二绝缘层D上形成图1C所示应用传统方法时典型会产生的空腔。
各种不同的方法都可用于平坦化衬底结构的方法。例如,可以采用先选择性湿蚀刻位于具有高高度差的区域,即电容器的上部的第二绝缘层D的预定厚度,于是可以减少高度差,然后将化学机械抛光(CMP)处理应用到衬底结构,用以平坦化。
图3为另一典型衬底结构的横截面图,其中绝缘层是根据本发明第二实施例形成在电容器上。
参照图3,许多电容器C形成在提供第一绝缘层30、接触塞302和蚀刻停止层303的衬底上。每一个电容器C都包含接触对应的接触塞302且具有圆柱形形状的下电极304,覆盖下电极304的介电层305,和形成在介电层305上的上电极306。电容器C是形成在典型的DRAM单元区域中,而非形成在外围区域中,因此,在单元区域和外围区域之间的边界,展现至少约10,000的高度差。
接着,通过PECVD法,在电容器C上,形成基于USG的绝缘层310。此时,基于USG的绝缘层310的沉积厚度应该小于高度差。当基于USG的绝缘层是在很大的高度差的状态下,通过执行PECVD法,形成在电容器上时,会有接缝产生。但是,根据第二实施例,基于USG的绝缘层310以相对减少的厚度形成,因此接缝的深度没有很深。
其次,在基于USG的绝缘层310上形成可流动绝缘层320。此时,在外围区域的可流动绝缘层320的高度高于电容器。即使由于基于USG的绝缘层310的形成而产生一点点接缝,但是在可流动绝缘层320形成之后,就不会有接缝产生。
如第一实施例的说明,可以使用当衬底结构以约60rpm到约1,000rpm的速度旋转时,用液体源,如HSQ或MSQ,涂布衬底结构的旋涂介电(SOD)法,形成可流动绝缘层320。此外,也可以使用采用反应源,如SiH4和H2O2的LPCVD法形成可流动绝缘层320。
可流动绝缘层320的形成是要经历过沉积处理和热处理。在沉积处理之后,执行热处理,以移除存在在已沉积的绝缘层320内部的杂质或水份,然后密化可流动绝缘层320。热处理是使用炉管热处理和快速热处理,在O2、O3、N2、N2或H2和O2的混合气体的气氛中进行。炉管热处理要在约200℃到约650℃的温度范围下执行超过约5分钟。快速热处理要在高于约300℃的温度下执行超过约1秒。下面,将可流动绝缘层320和基于USG的绝缘层310称为第二绝缘层,在图3中以″D″表示。
接着,通过蚀刻或抛光已沉积的第二绝缘层D,平坦化结果衬底结构。在此,用以平坦化衬底结构的方法和第一实施例所采用的方法相同。另一方面,根据本发明的第二实施例,也可以不需要此平坦化步骤。
图4为衬底结构的横截面图,其中绝缘层是根据本发明第三实施例形成在电容器上。
参照图4,多数电容器C形成在提供第一绝缘层401、接触塞401和蚀刻停止层403的衬底上。每一个电容器C都包含接触对应的接触塞402且具有圆柱形形状的下电极404,覆盖下电极404的介电层405,和形成在介电层405上的上电极406。电容器C是形成在典型的DRAM单元区域中,而非形成在外围区域中,从而在单元区域和外围区域之间的边界,展现至少10,000的高度差。
接着,使用PECVD法,在提供多个电容器C的衬底上,形成基于USG的绝缘层410。此时,形成的基于USG的绝缘层的厚度比单元区域和外围区域之间的高度差更厚。然后,透过蚀刻处理和/或抛光处理,基于USG的绝缘层410被平坦化。此时,当以传统方法形成上述基于USG的绝缘层410时,会产生接缝,其在平坦化处理之后还会造成空腔的形成。
根据本发明的第三实施例,可流动绝缘层420所形成足以埋藏空腔和平坦化结果衬底结构的厚度,即厚度范围从约200到约5,000。下面,将可流动绝缘层420和基于USG的绝缘层410称为第二绝缘层,在图4中以″D″表示。
因为有可流动绝缘层420的形成,所以不仅可以移除产生在基于USG的绝缘层410表面上的空腔,还可以移除缺陷,如平坦化处理,像化学机械抛光(CMP)处理期间所产生的刮痕。换言之,由于空腔所造成的桥的形成,和为了在第二绝缘层D上形成金属相互连接线而造成的缺陷,这些问题都可以解决。
如先前的实施例,可以采用反应源,如SiH4和H2O2的SOD法或LPCVD法,形成可流动绝缘层420。此外,可流动绝缘层420的形成也可通过沉积处理和热处理完成。
根据本发明,形成在单元区域的电容器具有很高的高度,以确保在高度集成和微型化的装置如DRAM中,有很高的电容值,因此展现在单元区域和外围区域之间有很大的高度差,而且在电容器上形成具有良好层稳定性的基于USG的绝缘层,及具有低温处理容许量和良好平坦化特性的可流动绝缘层。结果,可以防止包含电容器的底层,在低温处理期间劣化,及可以防止在平坦化处理期间,在后续的金属相互连接线之间形成桥。结果,有增加高度集成半导体装置产量的效果。
本申请书包含在2004年5月31日向韩国专利局提交的韩国专利申请第KR2004-0039228号的相关内容,此处将所有的内容都纳入参考。
本发明已对于特定较佳实施例详细说明,那些熟悉本项技术人士所做的各种不同的变化例和修正例,明显将不脱离本发明在后面的权利要求所界定的精神和范围。
主要装置符号说明
11                    底绝缘层
12,202,302,402     接触塞
13,203,303,403     蚀刻停止层
14,204,304,404     下电极
15,205,305,405     介电层
16,206,306,406     上电极
17                    底部薄层
18                    中间薄层
19                    顶部薄层
20                    空腔
201,301,401         第一绝缘层
210,320,420         可流动绝缘层
220,310,410         基于USG的绝缘层
D                     第二绝缘层

Claims (17)

1.一种半导体装置,包含:
形成在衬底的预定部分之上的电容器;
通过在包括衬底和电容器的结果衬底结构上堆叠可流动绝缘层和未掺杂的硅酸盐玻璃层而形成的绝缘层;及
形成在绝缘层上的金属相互连接线。
2.如权利要求1所述的半导体装置,其中可流动绝缘层是形成在结果结构上,而未掺杂的硅酸盐玻璃层则形成在可流动绝缘层上。
3.如权利要求1所述的半导体装置,其中未掺杂的硅酸盐玻璃层是形成在包括电容器的结果结构上,而可流动绝缘层则形成在未掺杂的硅酸盐玻璃层上。
4.如权利要求2所述的半导体装置,其中可流动绝缘层是通过采用将液体源材料涂布在旋转的衬底上,随后衬底再施以热处理的旋涂介电法得到。
5.如权利要求3所述的半导体装置,其中可流动绝缘层是通过采用将液体源材料涂布在旋转的衬底上,随后再施以热处理的旋涂介电法得到。
6.如权利要求2所述的半导体装置,其中可流动绝缘层是通过使用如四氢化硅(SiH4)和过氧化氢(H2O2)的反应源的低压化学气相沉积法得到。
7.如权利要求3所述的半导体装置,其中可流动绝缘层是通过使用如四氢化硅(SiH4)和过氧化氢(H2O2)的反应源的低压化学气相沉积法得到。
8.如权利要求4所述的半导体装置,其中液体源材料是氢倍半硅氧烷(HSQ)和甲基倍半硅氧烷(MSQ)其中之一。
9.如权利要求5所述的半导体装置,其中液体源材料是HSQ和MSQ其中之一。
10.一种半导体装置的制造方法,包含下列步骤:
在衬底的预定部分之上形成电容器;
通过在包括衬底和电容器的结果衬底结构上堆叠可流动绝缘层和未掺杂的硅酸盐玻璃层,形成绝缘层;及
在绝缘层上形成金属互连接线。
11.如权利要求10所述的方法,其中形成绝缘层的步骤包含下列步骤:
在结果衬底结构上形成厚度小于电容器的高度的可流动绝缘层;
通过执行等离子体增强化学气相沉积法,在可流动绝缘层上形成未掺杂的硅酸盐玻璃层;及
平坦化未掺杂的硅酸盐玻璃层和可流动绝缘层。
12.如权利要求10所述的方法,其中形成绝缘层的步骤包含下列步骤:
通过执行等离子体增强化学气相沉积法,在结果衬底结构上形成厚度小于电容器的高度的未掺杂的硅酸盐玻璃层;
在未掺杂的硅酸盐玻璃层上,形成可流动绝缘层;及
平坦化未掺杂的硅酸盐玻璃层和可流动绝缘层。
13.如权利要求10所述的方法,其中形成绝缘层的步骤包含下列步骤:
通过执行等离子体增强化学气相沉积法,在结果衬底结构上形成厚度大于电容器的高度的未掺杂的硅酸盐玻璃层;
平坦化未掺杂的硅酸盐玻璃层;及
在已平坦化的未掺杂的硅酸盐玻璃层上形成可流动绝缘层。
14.如权利要求10所述的方法,其中形成可流动绝缘层的步骤包含下列步骤:
用选择自氢倍半硅氧烷(HSQ)和甲基倍半硅氧烷(MSQ)的液体源材料,通过旋转衬底,以薄层形式涂布在衬底上;及
对涂布的薄层执行热处理。
15.如权利要求10所述的方法,其中形成可流动绝缘层的步骤包含下列步骤:
通过使用四氢化硅(SiH4)和过氧化氢(H2O2)的反应源的低压化学气相沉积法,沉积薄层;及
对薄层执行热处理过程。
16.如权利要求10所述的方法,其中热处理是通过采用炉热处理过程和快速热处理过程其中之一,在选择自由氧气(O2)、臭氧(O3)、氮气(N2)、一氧化二氮(N2O)及氢气(H2)和氧气(O2)的混合气体所组成的组的气氛中进行。
17.如权利要求10所述的方法,其中平坦化处理是通过蚀刻处理和抛光处理其中之一执行。
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US8999856B2 (en) 2011-03-14 2015-04-07 Applied Materials, Inc. Methods for etch of sin films
US9267739B2 (en) 2012-07-18 2016-02-23 Applied Materials, Inc. Pedestal with multi-zone temperature control and multiple purge capabilities
US9373517B2 (en) 2012-08-02 2016-06-21 Applied Materials, Inc. Semiconductor processing with DC assisted RF power for improved control
US9132436B2 (en) 2012-09-21 2015-09-15 Applied Materials, Inc. Chemical control features in wafer process equipment
US10256079B2 (en) 2013-02-08 2019-04-09 Applied Materials, Inc. Semiconductor processing systems having multiple plasma configurations
US9362130B2 (en) 2013-03-01 2016-06-07 Applied Materials, Inc. Enhanced etching processes using remote plasma sources
US9773648B2 (en) 2013-08-30 2017-09-26 Applied Materials, Inc. Dual discharge modes operation for remote plasma
KR20150034981A (ko) * 2013-09-27 2015-04-06 에스케이하이닉스 주식회사 반도체 장치의 제조 방법
US9520303B2 (en) 2013-11-12 2016-12-13 Applied Materials, Inc. Aluminum selective etch
US9299537B2 (en) 2014-03-20 2016-03-29 Applied Materials, Inc. Radial waveguide systems and methods for post-match control of microwaves
US9903020B2 (en) 2014-03-31 2018-02-27 Applied Materials, Inc. Generation of compact alumina passivation layers on aluminum plasma equipment components
US9309598B2 (en) 2014-05-28 2016-04-12 Applied Materials, Inc. Oxide and metal removal
US9496167B2 (en) 2014-07-31 2016-11-15 Applied Materials, Inc. Integrated bit-line airgap formation and gate stack post clean
US9613822B2 (en) 2014-09-25 2017-04-04 Applied Materials, Inc. Oxide etch selectivity enhancement
US9355922B2 (en) 2014-10-14 2016-05-31 Applied Materials, Inc. Systems and methods for internal surface conditioning in plasma processing equipment
US9966240B2 (en) 2014-10-14 2018-05-08 Applied Materials, Inc. Systems and methods for internal surface conditioning assessment in plasma processing equipment
US11637002B2 (en) 2014-11-26 2023-04-25 Applied Materials, Inc. Methods and systems to enhance process uniformity
US10224210B2 (en) 2014-12-09 2019-03-05 Applied Materials, Inc. Plasma processing system with direct outlet toroidal plasma source
US10573496B2 (en) 2014-12-09 2020-02-25 Applied Materials, Inc. Direct outlet toroidal plasma source
US11257693B2 (en) 2015-01-09 2022-02-22 Applied Materials, Inc. Methods and systems to improve pedestal temperature control
US9728437B2 (en) 2015-02-03 2017-08-08 Applied Materials, Inc. High temperature chuck for plasma processing systems
US20160225652A1 (en) 2015-02-03 2016-08-04 Applied Materials, Inc. Low temperature chuck for plasma processing systems
US9881805B2 (en) 2015-03-02 2018-01-30 Applied Materials, Inc. Silicon selective removal
US9691645B2 (en) 2015-08-06 2017-06-27 Applied Materials, Inc. Bolted wafer chuck thermal management systems and methods for wafer processing systems
US9741593B2 (en) 2015-08-06 2017-08-22 Applied Materials, Inc. Thermal management systems and methods for wafer processing systems
US9349605B1 (en) 2015-08-07 2016-05-24 Applied Materials, Inc. Oxide etch selectivity systems and methods
US10504700B2 (en) 2015-08-27 2019-12-10 Applied Materials, Inc. Plasma etching systems and methods with secondary plasma injection
US10889082B2 (en) 2016-04-20 2021-01-12 Sony Corporation Laminated structure and method for producing the same
US10522371B2 (en) 2016-05-19 2019-12-31 Applied Materials, Inc. Systems and methods for improved semiconductor etching and component protection
US10504754B2 (en) 2016-05-19 2019-12-10 Applied Materials, Inc. Systems and methods for improved semiconductor etching and component protection
US9865484B1 (en) 2016-06-29 2018-01-09 Applied Materials, Inc. Selective etch using material modification and RF pulsing
US10062575B2 (en) 2016-09-09 2018-08-28 Applied Materials, Inc. Poly directional etch by oxidation
US10629473B2 (en) 2016-09-09 2020-04-21 Applied Materials, Inc. Footing removal for nitride spacer
US10062585B2 (en) 2016-10-04 2018-08-28 Applied Materials, Inc. Oxygen compatible plasma source
US9934942B1 (en) 2016-10-04 2018-04-03 Applied Materials, Inc. Chamber with flow-through source
US9721789B1 (en) 2016-10-04 2017-08-01 Applied Materials, Inc. Saving ion-damaged spacers
US10546729B2 (en) 2016-10-04 2020-01-28 Applied Materials, Inc. Dual-channel showerhead with improved profile
US10062579B2 (en) 2016-10-07 2018-08-28 Applied Materials, Inc. Selective SiN lateral recess
US9947549B1 (en) 2016-10-10 2018-04-17 Applied Materials, Inc. Cobalt-containing material removal
US9768034B1 (en) 2016-11-11 2017-09-19 Applied Materials, Inc. Removal methods for high aspect ratio structures
US10163696B2 (en) 2016-11-11 2018-12-25 Applied Materials, Inc. Selective cobalt removal for bottom up gapfill
US10026621B2 (en) 2016-11-14 2018-07-17 Applied Materials, Inc. SiN spacer profile patterning
US10242908B2 (en) 2016-11-14 2019-03-26 Applied Materials, Inc. Airgap formation with damage-free copper
US10566206B2 (en) 2016-12-27 2020-02-18 Applied Materials, Inc. Systems and methods for anisotropic material breakthrough
US10403507B2 (en) 2017-02-03 2019-09-03 Applied Materials, Inc. Shaped etch profile with oxidation
US10431429B2 (en) 2017-02-03 2019-10-01 Applied Materials, Inc. Systems and methods for radial and azimuthal control of plasma uniformity
US10043684B1 (en) 2017-02-06 2018-08-07 Applied Materials, Inc. Self-limiting atomic thermal etching systems and methods
US10319739B2 (en) 2017-02-08 2019-06-11 Applied Materials, Inc. Accommodating imperfectly aligned memory holes
US10943834B2 (en) 2017-03-13 2021-03-09 Applied Materials, Inc. Replacement contact process
US10319649B2 (en) 2017-04-11 2019-06-11 Applied Materials, Inc. Optical emission spectroscopy (OES) for remote plasma monitoring
US10950500B2 (en) 2017-05-05 2021-03-16 Applied Materials, Inc. Methods and apparatus for filling a feature disposed in a substrate
US11276559B2 (en) 2017-05-17 2022-03-15 Applied Materials, Inc. Semiconductor processing chamber for multiple precursor flow
US11276590B2 (en) 2017-05-17 2022-03-15 Applied Materials, Inc. Multi-zone semiconductor substrate supports
US10497579B2 (en) 2017-05-31 2019-12-03 Applied Materials, Inc. Water-free etching methods
US10049891B1 (en) 2017-05-31 2018-08-14 Applied Materials, Inc. Selective in situ cobalt residue removal
US10920320B2 (en) 2017-06-16 2021-02-16 Applied Materials, Inc. Plasma health determination in semiconductor substrate processing reactors
US10541246B2 (en) 2017-06-26 2020-01-21 Applied Materials, Inc. 3D flash memory cells which discourage cross-cell electrical tunneling
US10727080B2 (en) 2017-07-07 2020-07-28 Applied Materials, Inc. Tantalum-containing material removal
US10541184B2 (en) 2017-07-11 2020-01-21 Applied Materials, Inc. Optical emission spectroscopic techniques for monitoring etching
US10354889B2 (en) 2017-07-17 2019-07-16 Applied Materials, Inc. Non-halogen etching of silicon-containing materials
US10170336B1 (en) 2017-08-04 2019-01-01 Applied Materials, Inc. Methods for anisotropic control of selective silicon removal
US10043674B1 (en) 2017-08-04 2018-08-07 Applied Materials, Inc. Germanium etching systems and methods
US10297458B2 (en) 2017-08-07 2019-05-21 Applied Materials, Inc. Process window widening using coated parts in plasma etch processes
US10283324B1 (en) 2017-10-24 2019-05-07 Applied Materials, Inc. Oxygen treatment for nitride etching
US10128086B1 (en) 2017-10-24 2018-11-13 Applied Materials, Inc. Silicon pretreatment for nitride removal
US10256112B1 (en) 2017-12-08 2019-04-09 Applied Materials, Inc. Selective tungsten removal
US10903054B2 (en) 2017-12-19 2021-01-26 Applied Materials, Inc. Multi-zone gas distribution systems and methods
US11328909B2 (en) 2017-12-22 2022-05-10 Applied Materials, Inc. Chamber conditioning and removal processes
US10854426B2 (en) 2018-01-08 2020-12-01 Applied Materials, Inc. Metal recess for semiconductor structures
US10964512B2 (en) 2018-02-15 2021-03-30 Applied Materials, Inc. Semiconductor processing chamber multistage mixing apparatus and methods
US10679870B2 (en) 2018-02-15 2020-06-09 Applied Materials, Inc. Semiconductor processing chamber multistage mixing apparatus
TWI766433B (zh) 2018-02-28 2022-06-01 美商應用材料股份有限公司 形成氣隙的系統及方法
US10593560B2 (en) 2018-03-01 2020-03-17 Applied Materials, Inc. Magnetic induction plasma source for semiconductor processes and equipment
US10319600B1 (en) 2018-03-12 2019-06-11 Applied Materials, Inc. Thermal silicon etch
US10497573B2 (en) 2018-03-13 2019-12-03 Applied Materials, Inc. Selective atomic layer etching of semiconductor materials
US10573527B2 (en) 2018-04-06 2020-02-25 Applied Materials, Inc. Gas-phase selective etching systems and methods
US10490406B2 (en) 2018-04-10 2019-11-26 Appled Materials, Inc. Systems and methods for material breakthrough
US10699879B2 (en) 2018-04-17 2020-06-30 Applied Materials, Inc. Two piece electrode assembly with gap for plasma control
US10886137B2 (en) 2018-04-30 2021-01-05 Applied Materials, Inc. Selective nitride removal
US10755941B2 (en) 2018-07-06 2020-08-25 Applied Materials, Inc. Self-limiting selective etching systems and methods
US10872778B2 (en) 2018-07-06 2020-12-22 Applied Materials, Inc. Systems and methods utilizing solid-phase etchants
US10672642B2 (en) 2018-07-24 2020-06-02 Applied Materials, Inc. Systems and methods for pedestal configuration
US11049755B2 (en) 2018-09-14 2021-06-29 Applied Materials, Inc. Semiconductor substrate supports with embedded RF shield
US10892198B2 (en) 2018-09-14 2021-01-12 Applied Materials, Inc. Systems and methods for improved performance in semiconductor processing
US11062887B2 (en) 2018-09-17 2021-07-13 Applied Materials, Inc. High temperature RF heater pedestals
US11417534B2 (en) 2018-09-21 2022-08-16 Applied Materials, Inc. Selective material removal
US11682560B2 (en) 2018-10-11 2023-06-20 Applied Materials, Inc. Systems and methods for hafnium-containing film removal
US11121002B2 (en) 2018-10-24 2021-09-14 Applied Materials, Inc. Systems and methods for etching metals and metal derivatives
US11437242B2 (en) 2018-11-27 2022-09-06 Applied Materials, Inc. Selective removal of silicon-containing materials
US11721527B2 (en) 2019-01-07 2023-08-08 Applied Materials, Inc. Processing chamber mixing systems
US10920319B2 (en) 2019-01-11 2021-02-16 Applied Materials, Inc. Ceramic showerheads with conductive electrodes
US11647624B2 (en) 2020-12-15 2023-05-09 Micron Technology, Inc. Apparatuses and methods for controlling structure of bottom electrodes and providing a top-support thereof

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5674773A (en) * 1996-03-15 1997-10-07 Vanguard International Semiconductor Corporation Method for planarizing high step-height integrated circuit structures
KR100211540B1 (ko) * 1996-05-22 1999-08-02 김영환 반도체소자의 층간절연막 형성방법
US6013583A (en) * 1996-06-25 2000-01-11 International Business Machines Corporation Low temperature BPSG deposition process
KR100238252B1 (ko) * 1996-09-13 2000-01-15 윤종용 Sog층 큐어링방법 및 이를 이용한 반도체장치의 절연막제조방법
US6551665B1 (en) * 1997-04-17 2003-04-22 Micron Technology, Inc. Method for improving thickness uniformity of deposited ozone-TEOS silicate glass layers
KR100256055B1 (ko) 1997-08-28 2000-06-01 윤종용 평탄화 개선을 위한 반도체 장치 제조 방법
KR100269317B1 (ko) * 1997-12-09 2000-12-01 윤종용 평탄화를위한반도체장치및그제조방법
US6025279A (en) * 1998-05-29 2000-02-15 Taiwan Semiconductor Manufacturing Company Method of reducing nitride and oxide peeling after planarization using an anneal
JP2000164716A (ja) * 1998-11-26 2000-06-16 Seiko Epson Corp 半導体装置及びその製造方法
TW429579B (en) * 1999-08-23 2001-04-11 Taiwan Semiconductor Mfg Manufacturing method of inter-layer dielectric
KR100362834B1 (ko) * 2000-05-02 2002-11-29 삼성전자 주식회사 반도체 장치의 산화막 형성 방법 및 이에 의하여 제조된 반도체 장치
KR100363093B1 (ko) * 2000-07-28 2002-12-05 삼성전자 주식회사 반도체 소자의 층간 절연막 평탄화 방법
US6432827B1 (en) * 2000-11-29 2002-08-13 United Microelectronics Corp. ILD planarization method
CN1173397C (zh) 2001-01-23 2004-10-27 联华电子股份有限公司 一种层间介电层平坦化的方法
KR100420117B1 (ko) * 2001-03-12 2004-03-02 삼성전자주식회사 수소 확산방지막을 포함하는 반도체 장치 및 그 제조 방법
KR100366639B1 (ko) * 2001-03-23 2003-01-06 삼성전자 주식회사 다공성 산화막 플러그에 의한 저저항 컨택 형성방법 및이를 이용한 반도체 장치의 형성방법
US20030036240A1 (en) * 2001-08-17 2003-02-20 Trivedi Jigish D. Method of simultaneous formation of local interconnect and gate electrode

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9607856B2 (en) 2013-03-05 2017-03-28 Applied Materials, Inc. Selective titanium nitride removal
CN108269807A (zh) * 2017-01-03 2018-07-10 联华电子股份有限公司 半导体元件的制作方法
CN108269807B (zh) * 2017-01-03 2021-06-22 联华电子股份有限公司 半导体元件的制作方法
CN109427786A (zh) * 2017-08-21 2019-03-05 联华电子股份有限公司 半导体存储装置及其制作工艺
US10818664B2 (en) 2017-08-21 2020-10-27 United Microelectronics Corp. Method of forming semiconductor memory device
CN109427786B (zh) * 2017-08-21 2021-08-17 联华电子股份有限公司 半导体存储装置及其制作工艺
CN107578996A (zh) * 2017-08-31 2018-01-12 长江存储科技有限责任公司 一种三维存储器及其平坦化方法
CN107578996B (zh) * 2017-08-31 2019-02-22 长江存储科技有限责任公司 一种三维存储器及其平坦化方法
CN109755243A (zh) * 2017-11-02 2019-05-14 联华电子股份有限公司 半导体元件及其制作方法
CN114975450A (zh) * 2022-06-22 2022-08-30 福建省晋华集成电路有限公司 半导体存储装置及其制作方法

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